JPS6248393B2 - - Google Patents
Info
- Publication number
- JPS6248393B2 JPS6248393B2 JP56064050A JP6405081A JPS6248393B2 JP S6248393 B2 JPS6248393 B2 JP S6248393B2 JP 56064050 A JP56064050 A JP 56064050A JP 6405081 A JP6405081 A JP 6405081A JP S6248393 B2 JPS6248393 B2 JP S6248393B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- silicon compound
- semiconductor substrate
- compound
- compound semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 150000003377 silicon compounds Chemical class 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 150000001875 compounds Chemical class 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000002844 melting Methods 0.000 claims description 8
- 230000008018 melting Effects 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 230000000873 masking effect Effects 0.000 claims 1
- 150000002739 metals Chemical class 0.000 claims 1
- 229910052750 molybdenum Inorganic materials 0.000 claims 1
- 229910052715 tantalum Inorganic materials 0.000 claims 1
- 229910052719 titanium Inorganic materials 0.000 claims 1
- 229910052721 tungsten Inorganic materials 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910016006 MoSi Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
本発明は電界効果トランジスタの製法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a field effect transistor.
同一出願人により化合物半導体基板に、800℃
程度の熱処理において安定な高融点金属けい素化
合物でゲート電極を形成し、これをマスクとして
イオン注入する電界効果トランジスタの製法が既
に出願されている。 Compound semiconductor substrate by the same applicant, 800℃
An application has already been filed for a method for manufacturing a field effect transistor in which a gate electrode is formed of a high melting point metal silicon compound that is stable under certain heat treatments, and ions are implanted using this as a mask.
この製法においては、たとえば化合物半導体と
してGaAs、高融点金属けい素化合物として
Ti0.3W0.7Si2を使用し、CF4＋５％O2でドライエ
ツチングしてゲート電極を形成するが、ゲート電
極はサイドエツチングされて、断面構造が、第１
図に示すように、テーパ型となる。その結果ゲー
ト電極の薄い部分を、次のソース ドレインコン
タクト領域形成用のイオン注入において打ち込ま
れたイオンが透過する。従つてこのゲート部の下
方にも高濃度の不純物拡散領域が形成される。こ
の不純物拡散領域は、特にイオン濃度ピーク部分
がゲート電極と接触するので、シヨツトキーゲー
トの逆方向耐圧が劣化する欠点を有する。 In this manufacturing method, for example, GaAs is used as a compound semiconductor, and silicon compound as a high melting point metal.
A gate electrode is formed using Ti 0 . 3 W 0 . 7 Si 2 and dry-etched with CF 4 +5% O 2 .
As shown in the figure, it is a tapered type. As a result, ions implanted in the next ion implantation for forming source/drain contact regions pass through the thin portion of the gate electrode. Therefore, a highly doped impurity diffusion region is also formed below this gate portion. This impurity diffusion region has the disadvantage that the reverse breakdown voltage of the Schottky gate is degraded because the ion concentration peak portion in particular contacts the gate electrode.
本発明の目的は上記欠点を解消することであ
る。 The aim of the invention is to eliminate the above-mentioned drawbacks.
本発明の上記目的は、逆テーパ型のシヨツトキ
ーゲート電極をマスクとしてイオン注入し、ソー
スおよびドレインのオーミツク接触用不純物拡散
領域を形成することによつて達成することができ
る。 The above object of the present invention can be achieved by performing ion implantation using a reverse tapered Schottky gate electrode as a mask to form impurity diffusion regions for ohmic contact of the source and drain.
本発明の逆テーパ型のシヨツトキーゲート電極
を形成するには、化合物半導体基板上に、高融点
金属けい素化合物のけい素含有量が、前記基板の
界面からこの金属けい素化合物の表面に向けて減
少するように、高融点金属けい素化合物層を形成
し、これを方向性を有するエツチング、たとえば
ガスエツチング、により表面方向からエツチング
することが便宜である。 To form the reverse tapered shot key gate electrode of the present invention, the silicon content of the high melting point metal silicon compound is distributed from the interface of the substrate to the surface of the metal silicon compound on the compound semiconductor substrate. It is expedient to form a layer of high-melting metal silicon compound and to etch it from the surface direction by directional etching, for example gas etching, such that the layer decreases toward the surface.
本発明の製法において、化合物半導体をGaAs
とし、高融点金属けい素化合物として、MoSi2，
WSi2，TiSi2，TaSi2またはTi0.3W0.7Si2を使用す
ることができる。これらのけい素化合物はけい素
含有量が多い程エツチング速度が大きいので、例
えば化合物半導体の界面に近い領域においてけい
素原子比を２とし、ゲート電極の表面においてけ
い素原子比をゼロとすれば、方向性を有するガス
イオンエツチングによつて、第２図に示すような
逆テーパ型ゲート電極を形成することができる。 In the manufacturing method of the present invention, the compound semiconductor is GaAs
As a high melting point metal silicon compound, MoSi 2 ,
WSi 2 , TiSi 2 , TaSi 2 or Ti 0.3 W 0.7 Si 2 can be used . The etching rate of these silicon compounds increases as the silicon content increases. For example, if the silicon atomic ratio is set to 2 in the region near the interface of the compound semiconductor, and the silicon atomic ratio is set to 0 at the surface of the gate electrode, A reverse tapered gate electrode as shown in FIG. 2 can be formed by directional gas ion etching.
実施例
化合物半導体をGaAsとし、ゲート材料として
Ti0.3W0.7Sixを使用し、第３図に示すように、
GaAsとの界面d0から表面d1に向けてSi原子比ｘ
が２からゼロに減少するようにマルチ・ターゲツ
ト・スパツター法等によつてけい素化合物層を付
着させた。次にCF4＋10％O2のガス圧を3.5Paと
して、出力100Wでガスイオンエツチングした。
このときのエツチング速度は、第４図に示すよう
に、Si2の領域はSi0の領域のほぼ３倍である。こ
うしてパターニングされたゲート電極は、第２図
に示すように、テーパ角θが約75゜であつた。こ
れに加圧電圧175KeV、ドーズ量1.7×1013／cmで
Si+を注入した。このときゲート電極の陰になつ
た部分にもイオンが注入されるが、n+領域、特
にピーク濃度部分が電極の界面まで達しない。従
つてこの電界効果トランジスタのシヨツトキー逆
方向耐圧は少くとも5V、通常は８〜9Vであつ
た。従来のゲート電極がテーパ型である場合にシ
ヨツトキー逆方向耐圧が2.5V程度であるのと比
べて、この値ははるかに大きい。このように、本
発明の電界効果トランジスタは動作の安定性が優
れていることを示した。Example Using GaAs as a compound semiconductor and using it as a gate material
Using Ti 0.3 W 0.7 Si x , as shown in Figure 3 ,
Si atomic ratio x from the interface d 0 with GaAs to the surface d 1
A silicon compound layer was deposited by a multi-target sputtering method or the like such that the number decreased from 2 to zero. Next, gas ion etching was performed using CF 4 +10% O 2 at a gas pressure of 3.5 Pa and an output of 100 W.
At this time, as shown in FIG. 4, the etching rate in the Si 2 region is approximately three times that in the Si 0 region. The gate electrode thus patterned had a taper angle θ of about 75°, as shown in FIG. This was applied with a voltage of 175KeV and a dose of 1.7×10 13 /cm.
Si + was injected. At this time, ions are also implanted into the shadowed portion of the gate electrode, but the n + region, especially the peak concentration portion, does not reach the electrode interface. Therefore, the shot key reverse breakdown voltage of this field effect transistor was at least 5V, and usually 8 to 9V. This value is much larger than the Schottky reverse breakdown voltage of about 2.5V when the conventional gate electrode is tapered. Thus, the field effect transistor of the present invention was shown to have excellent operational stability.
又、上記実施例においては、GaAs界面d0から
表面d1に向けて、ゲート電極となるけい素化合物
のSi原子比Ｘが２からゼロに減少するよう形成さ
れており、面積の大きいゲート電極上部において
Si含有量が少ない。そのためゲート電極全体のSi
含有量が少なくなり、その結果ゲート電極の抵抗
値が低減されるので、装置の特性が向上する。
又、該ゲート電極の材料としてはイオン注入後の
不純物活性化の熱処理に耐える高融点金属けい素
化合物等の使用が好ましい。 In addition, in the above embodiment, the Si atomic ratio X of the silicon compound forming the gate electrode decreases from 2 to zero from the GaAs interface d 0 to the surface d 1 , and the gate electrode has a large area. at the top
Low Si content. Therefore, the Si of the entire gate electrode
Since the content is reduced and the resistance value of the gate electrode is reduced as a result, the characteristics of the device are improved.
As the material for the gate electrode, it is preferable to use a high melting point metal silicon compound that can withstand heat treatment for impurity activation after ion implantation.
第１図は従来の製法によるテーパ型ゲート電極
を有する電界効果トランジスタの要部断面図であ
り、第２図は本発明の製法による逆テーパ型ゲー
ト電極を有する電界効果トランジスタの要部断面
図であり、第３図は本発明の製法によるゲート電
極の厚みとSi原子比との関係を示すグラフであ
り、第４図は本発明の製法によるゲート電極のSi
原子比とガスイオンエツチング速度との関係を示
すグラフである。
１……半導体基板、２……ゲート電極、３……
イオン濃度のピーク部分。
FIG. 1 is a sectional view of a main part of a field effect transistor having a tapered gate electrode manufactured by a conventional manufacturing method, and FIG. 2 is a sectional view of a main part of a field effect transistor having a reverse tapered gate electrode manufactured by a manufacturing method of the present invention. 3 is a graph showing the relationship between the thickness and Si atomic ratio of the gate electrode produced by the method of the present invention, and FIG. 4 is a graph showing the relationship between the thickness of the gate electrode produced by the method of the present invention and the Si atomic ratio.
3 is a graph showing the relationship between atomic ratio and gas ion etching rate. 1... Semiconductor substrate, 2... Gate electrode, 3...
Peak part of ion concentration.
Claims (1)
合物であつて、そのけい素含有量が該化合物半導
体基板界面近傍においては大であり、上方になる
に従つて該けい素含有量が小となるように高融点
金属けい素化合物層を形成し、方向性を有するエ
ツチングを施して逆テーパー型のシヨツトキゲー
ト電極を形成する工程と、次に 該逆テーパー型のシヨツトキゲート電極をマス
クとしてイオン注入し、ソースおよびドレインの
オーミツク接触用高濃度不純物拡散領域を形成す
る工程とを含むことを特徴とする電界効果トラン
ジスタの製造方法。 ２ 該化合物半導体基板がGaAsであり、該けい
素化合物がMo，Ｗ，Ti、およびTaの少なくとも
いずれか一つの金属のけい素化合物であり、注入
イオンがSi+であることを特徴とする特許請求の
範囲第１項記載の電界効果トランジスタの製造方
法。[Scope of Claims] 1. A high melting point metal silicon compound is deposited on a compound semiconductor substrate, the silicon content of which is high near the interface of the compound semiconductor substrate, and increases as the silicon content increases upward. A step of forming a high melting point metal silicon compound layer so that the content is small and performing directional etching to form a reverse tapered shot gate electrode, and then masking the reverse tapered shot gate electrode. 1. A method of manufacturing a field effect transistor, comprising the steps of: performing ion implantation as a step to form a highly concentrated impurity diffusion region for ohmic contact between a source and a drain. 2. A patent characterized in that the compound semiconductor substrate is GaAs, the silicon compound is a silicon compound of at least one of the metals Mo, W, Ti, and Ta, and the implanted ions are Si + A method for manufacturing a field effect transistor according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6405081A JPS57180184A (en) | 1981-04-30 | 1981-04-30 | Manufacturing method for fet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6405081A JPS57180184A (en) | 1981-04-30 | 1981-04-30 | Manufacturing method for fet |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57180184A JPS57180184A (en) | 1982-11-06 |
| JPS6248393B2 true JPS6248393B2 (en) | 1987-10-13 |
Family
ID=13246873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6405081A Granted JPS57180184A (en) | 1981-04-30 | 1981-04-30 | Manufacturing method for fet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57180184A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60219765A (en) * | 1984-04-16 | 1985-11-02 | Mitsubishi Electric Corp | Schottky barrier electrode |
| JPS61220376A (en) * | 1985-03-26 | 1986-09-30 | Sumitomo Electric Ind Ltd | Schottky gate field-effect transistor and manufacture thereof |
| DE3751278T2 (en) * | 1986-12-11 | 1996-01-25 | Gte Laboratories Inc | Transistor composed of a semiconductor material and a conductive material. |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5194775A (en) * | 1975-02-19 | 1976-08-19 | ||
| JPS5197383A (en) * | 1975-02-21 | 1976-08-26 |
-
1981
- 1981-04-30 JP JP6405081A patent/JPS57180184A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5194775A (en) * | 1975-02-19 | 1976-08-19 | ||
| JPS5197383A (en) * | 1975-02-21 | 1976-08-26 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57180184A (en) | 1982-11-06 |
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