JPS6247300U - - Google Patents
Info
- Publication number
- JPS6247300U JPS6247300U JP6273685U JP6273685U JPS6247300U JP S6247300 U JPS6247300 U JP S6247300U JP 6273685 U JP6273685 U JP 6273685U JP 6273685 U JP6273685 U JP 6273685U JP S6247300 U JPS6247300 U JP S6247300U
- Authority
- JP
- Japan
- Prior art keywords
- audio signal
- address
- processing device
- time difference
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005236 sound signal Effects 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 1
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は第１図におけるメモリの書込み及び読出
しアドレスの位置関係を示す図、第３図は疑似ス
テレオ装置においてオーデイオ信号の遅延を例え
ばデイジタル的に行なつた場合の構成を示すブロ
ツク図である。
主要部分の符号の説明、２……メモリ、３……
書込みアドレス発生回路、４，５……マルチプレ
クサ、１２……読出しアドレス発生回路、１３…
…加算器、１４……増分アドレスカウンタ、１５
，１６……電圧制御増幅器、１８……データ変換
器。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a diagram showing the positional relationship of memory write and read addresses in FIG. 1, and FIG. 3 is a block diagram showing the configuration when audio signals are delayed, for example, digitally in a pseudo stereo system. . Explanation of symbols of main parts, 2...Memory, 3...
Write address generation circuit, 4, 5... Multiplexer, 12... Read address generation circuit, 13...
... Adder, 14 ... Incremental address counter, 15
, 16... Voltage control amplifier, 18... Data converter.
Claims (1)
々所定の時間差を持つ複数のオーデイオ信号を出
力する遅延回路を含むオーデイオ信号処理装置で
あつて、前記複数のオーデイオ信号間の時間差に
応じた制御信号を出力する手段と、前記制御信号
に応じて前記複数のオーデイオ信号の各信号レベ
ルを調整する手段とを備えたことを特徴とするオ
ーデイオ信号処理装置。 (2) 前記遅延回路は、前記入力アナログオーデ
イオ信号をデイジタル化するＡ／Ｄ（アナログ／
デイジタル）変換器と、書込み及び読出し自在な
メモリと、前記Ａ／Ｄ変換器の出力データを前記
メモリの書込みアドレスで指定されたアドレスに
書き込みかつ互いに前記時間差に対応したアドレ
ス分だけ異なる複数の読出しアドレスで指定され
たアドレスから記憶データを読み出すべく制御す
るメモリ制御手段とを有することを特徴とする実
用新案登録請求の範囲第１項記載のオーデイオ信
号処理装置。[Claims for Utility Model Registration] (1) An audio signal processing device including a delay circuit that outputs a plurality of audio signals each having a predetermined time difference based on an input analog audio signal, An audio signal processing device comprising: means for outputting a control signal according to a time difference; and means for adjusting each signal level of the plurality of audio signals according to the control signal. (2) The delay circuit is an A/D (analog/digital converter) that digitizes the input analog audio signal.
a digital) converter, a memory that can be freely written and read, and a plurality of readout devices that write output data of the A/D converter to an address specified by a write address of the memory and that are different from each other by an address corresponding to the time difference. 2. The audio signal processing device according to claim 1, further comprising memory control means for controlling the reading of stored data from an address specified by an address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6273685U JPS6247300U (en) | 1985-04-26 | 1985-04-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6273685U JPS6247300U (en) | 1985-04-26 | 1985-04-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6247300U true JPS6247300U (en) | 1987-03-23 |
Family
ID=30897291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6273685U Pending JPS6247300U (en) | 1985-04-26 | 1985-04-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6247300U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50115502A (en) * | 1974-02-20 | 1975-09-10 | ||
| JPS5645360A (en) * | 1979-09-14 | 1981-04-25 | Chiyoda Koki:Kk | Grinding device for lens |
| JPS61130000A (en) * | 1984-11-28 | 1986-06-17 | Nippon Gakki Seizo Kk | Acoustic image position controlling device |
-
1985
- 1985-04-26 JP JP6273685U patent/JPS6247300U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50115502A (en) * | 1974-02-20 | 1975-09-10 | ||
| JPS5645360A (en) * | 1979-09-14 | 1981-04-25 | Chiyoda Koki:Kk | Grinding device for lens |
| JPS61130000A (en) * | 1984-11-28 | 1986-06-17 | Nippon Gakki Seizo Kk | Acoustic image position controlling device |
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