JPS5984645U - histogram creation device - Google Patents
histogram creation deviceInfo
- Publication number
- JPS5984645U JPS5984645U JP17851082U JP17851082U JPS5984645U JP S5984645 U JPS5984645 U JP S5984645U JP 17851082 U JP17851082 U JP 17851082U JP 17851082 U JP17851082 U JP 17851082U JP S5984645 U JPS5984645 U JP S5984645U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- input
- address
- histogram creation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Image Processing (AREA)
- Image Analysis (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は本考案の一実施例であるヒストグラム作成装置のブ
ロック図を示す。
図において、１はディジタル入力信号、２はア
′ドレス信号、３は制御信号、４はゲート信号、５
は増加パルス、６はデータカウンター用制御信号、７は
アドレスカウンター用制御信号、８はアドレスカウンタ
ー出力信号、９はＲＡＭ入力信号、１０はＲＡＭ出力信
号、１１はヒストグラム出力データ、１２はゲート回路
、１３はヒストグラム作成テーブル回路、１４はＲＡＭ
、、１５はアドレスカウンター回路、１６はデータカウ
ンタ回路、。
１７は制御回路、１８は書き込み信号をそれぞれ示す。The figure shows a block diagram of a histogram creation device that is an embodiment of the present invention. In the figure, 1 is the digital input signal and 2 is the digital input signal.
'dress signal, 3 is control signal, 4 is gate signal, 5
is an increasing pulse, 6 is a data counter control signal, 7 is an address counter control signal, 8 is an address counter output signal, 9 is a RAM input signal, 10 is a RAM output signal, 11 is histogram output data, 12 is a gate circuit, 13 is a histogram creation table circuit, 14 is a RAM
,, 15 is an address counter circuit, and 16 is a data counter circuit. Reference numeral 17 indicates a control circuit, and 18 indicates a write signal.
Claims (1)
る際に、ＡＩＤ変換回路によってディジタル信号に変換
した入力アナログ信号をアドレス信号として入力し、出
力信号として、入力アドレスの濃度値を持つ信号の個数
が得られるようにするためのヒストグラム作成テーブル
回路と、前記テーブルの更新を行なうための制御回路と
、前記テーブル内のデータを増加させるために使用する
データカウンタ回路と、初期状態において、前記テーブ
ル内のデータを０”にセットするためのアドレスカウン
タ回路とを用いて、ヒストグラムを作成することを特徴
とするヒストグラム作成装置。When creating a density distribution (histogram) of an input analog signal, the input analog signal converted to a digital signal by an AID conversion circuit is input as an address signal, and the number of signals having the density value of the input address is obtained as an output signal. a histogram creation table circuit for updating the table; a control circuit for updating the table; a data counter circuit for increasing the data in the table; and an address counter circuit for setting 0'' to 0''.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17851082U JPS5984645U (en) | 1982-11-26 | 1982-11-26 | histogram creation device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17851082U JPS5984645U (en) | 1982-11-26 | 1982-11-26 | histogram creation device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5984645U true JPS5984645U (en) | 1984-06-07 |
Family
ID=33307433
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17851082U Pending JPS5984645U (en) | 1982-11-26 | 1982-11-26 | histogram creation device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5984645U (en) |
-
1982
- 1982-11-26 JP JP17851082U patent/JPS5984645U/en active Pending
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