JPS6247266B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sound reporting device for bass manufacturers and the like that generates a predetermined rhythm sound.

In recent years, jogging as a sport has become popular to the general public for the purpose of improving health. Also,
On the other hand, bass manufacturers have been put into practical use that generate electronic sounds at a certain rhythm to facilitate jogging. The above-mentioned bass manufacturers are capable of varying the speed of the rhythm that is generated, allowing the user to adjust it arbitrarily to suit each individual's ability. Conventional pacemakers can adjust the speed of the rhythm, but the rhythm is constant from start to finish, so if you start running in time with that rhythm, it puts a sudden strain on your heart, which can be harmful to your health. There was a problem that it was not good for me.

The present invention has been made in view of the above points, and the sound is emitted at a slow rhythm at the start, and thereafter the sound rhythm gradually becomes faster, thereby preventing a sudden increase in the burden on the heart. The purpose of the present invention is to provide a sound alarm device that is extremely useful for improving health.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of implementation in an electronic wristwatch. In FIG. 1, 1 is an oscillation circuit that generates a reference signal for a clock. The reference signal outputted from this oscillation circuit 1 is sent to a frequency divider circuit 2, frequency-divided into a signal with a period of 1 second, and inputted to a counter 3. This clock hour part 3 is the input 1
The time information of "hour", "minute", and "second" is obtained by counting the second signal, and the time information is sent to the digital display section 5 via the display switching circuit 4. Further, from the frequency dividing circuit 2, the output line a is output at 2 Hz, for example.
The signal is extracted and input to the timing generation circuit 6. For example, the timing generation circuit 6 generates signals of 1/6Hz, 1/3Hz, 1/2 according to the signal from the frequency divider circuit 2.
Timing signals of Hz, 1Hz, and 2Hz are generated and input to AND circuits 7a to 7e, respectively. In addition, the timing signal generation circuit 6 outputs 40, 60, and 80 shots per minute.
100 pulse signals 40P/1M, 60P/
1M, 80P/1M, and 100P/1M are generated and input to AND circuits 8a to 8d, respectively. Further, _S1 is a pace selection switch, _S2 is a start/stop switch, and _S3 is a changeover switch, and each operation output is input to one-shot circuits 9, 10, and 11, respectively.
The output of the one-shot circuit 9 is inputted to, for example, a quinary pace counter 12 as a count-up signal. Furthermore, each count output of "0" to "4" of this pace counter 12 is sent to the display switching circuit 4 and also to the AND circuit 7.
It is input to a to 7e. The outputs of these AND circuits 7a to 7e are input as count-up signals to, for example, a decimal counter 15 via an OR circuit 13 and an AND circuit 14. The carry output of this counter 15 is inputted via an OR circuit 16 to a count signal input terminal of a quinary up/down counter 17. Each count output of "1" to "4" of this up-down counter 17 is
The signals are input as gate signals to AND circuits 8a to 8d. The outputs of these AND circuits 8a to 8d are sent to a sound alarm device 19 via an OR circuit 18. On the other hand, the output of the one-shot circuit 11 is input to the trigger terminal T of the T-type flip-flop 21. This flip-flop 21 performs an inverting operation every time a trigger signal is input, and its Q side output is sent as a switching signal to the display switching circuit 4 and is also input to AND circuits 8a to 8d.
Further, the Q side output of the flip-flop 21 is inputted to an AND circuit 22 together with the output of the one shot circuit 10. The output of the AND circuit 22 is input to the trigger terminal T of the T-type flip-flop 23 and also to the AND circuits 24 and 25. The side output of the flip-flop 23 is input to the AND circuit 25, and the Q side output is input to the AND circuit 25.
4 and the up-down counter 17
It is sent as a count up command to The outputs of the AND circuits 24 and 25 are input to the set terminal S of the RS flip-flop 27 via the OR circuit 26 and also to the OR circuit 16. Further, the count outputs of "0" and "4" from the up-down counter 17 are inputted to the reset terminal R of the flip-flop 27 via an OR circuit 28. Then, the Q side output of the flip-flop 27 is input to the AND circuit 14.

Next, the operation of the present invention configured as described above will be explained. The counting circuit 3 constantly counts the one-second signal output from the frequency dividing circuit 2 to obtain time information for the current time. This time information is selected by the display switching circuit 4 when the flip-flop 4 is reset, and sent to the display section 5 for display. However, in the above time display mode,
When the changeover switch _S3 is operated, a one-shot pulse is output from the one-shot circuit 11, and the flip-flop 21 is set to function as a pacemaker. That is, when the flip-flop 21 is set, the display switching circuit 4 is first switched by its Q-side output, and the count contents of the pace counter 12 are sent to the display section 5 and displayed. The contents of the pace counter 12 are as follows:
This corresponds to the time required for the rhythm speed to reach a predetermined value, and is arbitrarily set by the pace selection switch _S1 . In this case, the time it takes for the rhythm speed to reach a predetermined value becomes shorter as the content of the pace counter 12 becomes larger. The Q side output of the flip-flop 21 is input to an AND circuit 22 in preparation for operation of the start/stop switch _S2 . Start/stop switch S ₂ in this state
When operated, a one-shot pulse is output from the one-shot circuit 10 and inputted to the trigger terminal T of the flip-flop 23 via the AND circuit 22. As a result, the flip-flop 23 is set and the Q side output becomes "1", an up-count command is sent to the up-down counter 17, and the gate of the AND circuit 24 is opened, and the output of the AND circuit 22 is transferred to the AND circuit 24 and the gate of the AND circuit 24. The signal is input to the up-down counter 17 via the OR circuit 16. As a result, the contents of the up-down counter 17 count up from "0" to "1", and the "1" count output is input to the AND circuit 8a. Also, at this time, since the set output signal "1" of the flip-flop 21 is given to the AND circuit 8a, when the content of the up-down counter 17 counts up to "1", the AND circuit 8a
gate opens, and the pulse signal 40P/1M, which is outputted from the timing signal generation circuit 6 at 40 times per minute, is selected and sent to the sound alarm device 19 via the OR circuit 18. As a result, at the start, the alarm operation is performed at a slow rhythm of 40 times per minute. Further, the output of the AND circuit 24 is inputted to the set terminal S of the flip-flop 27 via the OR circuit 26. As a result, flip-flop 27 is set and the gate of AND circuit 14 is opened. Therefore, if the content of the pace counter 12 is now set to "0", the gate of the AND circuit 7a is opened by the "0" count output, and the 1/6Hz output from the timing signal generation circuit 6 is generated. The signal is selected and input to the decimal counter 15 via the OR circuit 13 and the AND circuit 14. This counter 15 outputs a carry signal after counting 10 input 1/6 Hz signals, that is, after 60 seconds have elapsed. This carry signal is sent to the up-down counter 17 via the OR circuit 16, and its contents are counted up to "2". When the contents of the up-down counter 17 count up to "2", the gate of the AND circuit 8b is opened by the "2" count output, and the pulse signal 60P/min is output from the timing signal generation circuit 6.
1M is selected and sent to the alarm device 19 via the OR circuit 18. As a result, the rhythm of the alarm will increase from the previous 40 beats per minute to 60 beats per minute. Thereafter, a carry signal is output from the counter 15 every 60 seconds in the same manner, and the contents of the up-down counter 17 are sequentially counted up. As the contents of the up-down counter 17 count up, the timing signal 80P/1M is output from the timing signal generation circuit 6.
100P/1M are sequentially selected and sent to the alarm device 19 via the OR circuit 18. In this way, the rhythm of the alarm is 40 seconds per minute, every 60 seconds, as shown in Figure 2a.
The rhythm gradually increases from 1 to 60, then 80, and then 100 times. When the contents of the up-down counter 17 are counted up to "4", the "4" count output is inputted to the reset terminal R of the flip-flop 27 via the OR circuit 28. Therefore, the flip-flop 27 is reset, its Q side output becomes "0", and the gate of the AND circuit 14 is closed. Therefore, input to the counter 15 is prohibited, and the count-up operations of the counter 15 and up-down counter 17 are stopped.
The count content of the up-down counter 17 is maintained at "4". Therefore, from then on, the rhythm of the sound is maintained at a rhythm of 100 beats per minute, or the steady rhythm of jogging.

Therefore, when finishing jogging, the start/stop switch _S2 is operated again. By operating this switch _S2 , a one-shot pulse is output from the one-shot circuit 10, and the flip-flop 23 is inverted, that is, reset, and its Q
The side output becomes "0" and the output becomes "1". When the Q side output of this flip-flop 23 becomes "0", the up-down counter 17 becomes
Switch to down count mode. Furthermore, when the side output of the flip-flop 23 becomes "1", the gate of the AND circuit 25 opens and its output becomes "1".
The flip-flop 27 is then set.
As a result, the Q output of the flip-flop 27 becomes "1", the gate of the AND circuit 14 is opened, and the 1/1 output from the timing signal generation circuit 6 is output.
A 6 Hz timing signal is input to the counter 15, and the operation of the counter 15 is restarted. A carry signal is outputted by the count-up operation of the counter 15, and is inputted to the up-down counter 17 via the OR circuit 16. At this time,
This counter 17 is in a down count mode, so when the carry signal is input from the counter 15, its contents are incremented by "-1" to become "3", and the "3" count output becomes "1". .
As a result, the gate of the AND circuit 8c is opened, and the timing signal 80P/1M, which is outputted from the timing signal generation circuit 6 at 80 times per minute, is selected and sent to the sound alarm device 19 via the OR circuit 18. As a result, the rhythm of the alarm signal changed from the previous rhythm of 100 times per minute to a rhythm of 80 times per minute. Thereafter, a carry signal is output from the counter 15 every 60 seconds in the same manner, and the contents of the up-down counter 17 are counted down sequentially, and the timing signal sent to the sound alarm device 19 is sequentially decreased to 60P/1M and 40P/1M. do. Therefore, the rhythm of the alarm signal decreases sequentially from 100 times per minute to 80 times, 60 times, and 40 times per minute every 60 seconds, as shown in Figure 2a. When the content of the up-down counter 17 reaches "0", the AND circuit 8a
All the gates 8d to 8d are closed, input to the sound alarm device 19 is prohibited, and the sound alarm operation is stopped. Further, the “0” count output of the up-down counter 17 is sent to the flip-flop 27 via an OR circuit 28.
It is input to the reset terminal R of the flip-flop 27 and resets the flip-flop 27. Therefore, the Q side output of the flip-flop 27 becomes "0", the gate of the AND circuit 14 is closed, input to the counter 15 is prohibited, and the counting operations of the counter 15 and the up/down counter 17 are stopped.

In this way, the content of the pace counter 12 is set to "0".
If set to , the rhythm of the alarm will change sequentially at 60 second intervals at the start and stop times.
As the setting content of the pace counter 12 is increased, the change period of the rhythm of the warning sound becomes faster. That is, when the content of the pace counter 12 is set to "1" by operating the pace selection switch _S1 , the AND circuit 7 is output by the "1" count output.
The gate b opens, and the 1/3 Hz timing signal output from the timing signal generation circuit 6 is selected and input to the AND circuit 14 via the OR circuit 13. For this reason, the start/stop switch S ₂
When the gate of the AND circuit 14 is opened by the operation of , the counter 15 counts up by the 1/3 Hz signal and outputs a carry signal at 30 second intervals. Therefore, the up-down counter 17 is 30.
It counts up or down at intervals of seconds, and the rhythm of the alarm changes at intervals of 30 seconds at the start and stop times, as shown in Figure 2b. Thereafter, by sequentially counting up the contents of the pace counter 12 in the same manner, the timing signal generation circuit 6 outputs 1/2 Hz, 1 Hz, 2
Hz timing signal is selected and the rhythm of the alarm becomes even faster as shown in Figure 2c, 20 seconds, 10 seconds.
It will change at intervals of seconds, 5 seconds, etc.

In the above embodiment, an independent notification device is provided, but a sound notification device used for a time signal or an alarm of a clock may be used.

Further, the rhythm sound may be automatically stopped after running for a predetermined time or a time set in advance by the user. Furthermore, the rhythm speed is not limited to this example; for example, 40P/
The user may select 1M, 60P/1M, 80P/1M, and 100P/1M, respectively.

Furthermore, in the above embodiment, when the content of the pace counter is "0", the pace is increased every 60 seconds, and the content is "1".
I set the pace to increase every 30 seconds when
The value is arbitrary, and the user may directly set the time interval.

As described above, according to the present invention, the operation is started by the first operation of the start/stop switch _S2 , and the timer means 15 outputs a time-up signal every time a predetermined period of time elapses; Changing means _S1 , 12, 7a to 7e for changing the time interval at which signals are output; and counting means 1 for counting time-up signals from the timer means.
7, timing signal output means 6, 8a to 8d for selectively outputting timing signals of low cycle to high cycle according to the count value of the counting means; Since the alarm generating means 19 is provided with a timing signal and generates noise according to the period of the supplied timing signal, the alarm is generated at a slow rhythm at the start, and then the alarm is sequentially started. The rhythm of the sound is now faster, and the base up speed of the rhythm of the sound can be arbitrarily selected according to the user's physical condition, ability, etc., which prevents a sudden increase in the burden on the heart and improves health. It is possible to provide a sound alarm device that is extremely useful for promotion.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention, and FIG. 1 is a circuit diagram, and FIGS. 2 a to 2 c are diagrams for explaining changes in the rhythm of the alarm sound. 6...timing generation circuit, 9, 10, 11...
...One-shot circuit, 12...Pace counter,
15...Counter, 17...Up-down counter, 19...Sound warning device, _S1 ...Pace selection switch, _S2 ...Start/stop switch, _S3 ...
Changeover switch.

Claims (1)

[Scope of Claims] 1. A start/stop switch; the first switch operation of the start/stop switch starts the generation of pace sound, and the second switch operation of the start/stop switch starts generating the pace sound. A sound alarm device that stops sound generation includes a timer means that starts operation upon the first operation of the start/stop switch and outputs a time-up signal every time a predetermined time elapses, and a timer means that outputs the time-up signal. a changing means for changing the time interval of the timer; a counting means for counting the time-up signal from the timer means; and a timing signal for selectively outputting a timing signal for a higher period in order from a lower period according to the count value of the counting means. and an alarm sound generating means that is supplied with a timing signal output from the timing signal output means and generates an alarm sound according to the period of the supplied timing signal, and the changing means A sound reporting device characterized in that the time from the output of the low-cycle timing signal to the output of the high-cycle timing signal is changed by.