JPH0142077Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a digital watch with a counter.

[Prior Art] For example, there is a device that counts and displays the number of times a religious theme has been chanted, as disclosed in Japanese Utility Model Application No. 55-90993. This counts pulses with a period that matches the speed of chanting the daimoku and displays it as the number of times the daimoku is chanted. Generally, religious believers aim to chant 1 million times.
The one above can also display up to the millionth digit.

[Problem that the invention attempts to solve]

The above-mentioned device was used only as a counter for the number of times the chanting was performed, and was useless except when chanting the chant.
Therefore, there is a need for something that can also be used as a clock, displaying the time at all times, and functioning as a chanting counter only when chanting. However, a typical digital clock that displays hours, minutes, and seconds only has six digits and can only display up to 100,000 digits. In order to display up to 1 million digits, one more digit display pattern must be added.

Furthermore, since the above-mentioned device does not have a display section for displaying the period of the selected pulse, it is difficult to tell which period is currently set, which is inconvenient.

The present invention is designed to both display the counting period and display the most significant digit of the counted value.

[Problem that the invention attempts to solve]

This invention selectively displays the time and count value on the digital display, and when the time is displayed, the counting cycle is displayed, and when the count value is displayed, the most significant digit that can be displayed on the digital display is displayed. Furthermore, a display section is provided to display the higher order digits.

〔Example〕

In FIG. 1, reference numeral 1 denotes a digital display section consisting of a six-digit day-shaped display segment, which displays the output of either a clock circuit or a counting circuit, which will be described later. 2a, 2b, and 2c are display sections for selectively displaying the counting period and the value in the millionth place (up to 3 million). 3 is a mode switch for selecting time display and counting display, 4 is a counting cycle selection switch,
5 is a counting start/stop switch.

FIG. 2 shows an example of a circuit configuration, in which 6 is a crystal oscillator, 7 is a frequency divider, and 8 is a clock circuit for hours, minutes, and seconds. Reference numeral 9 denotes a selection circuit that selects one of the 0.5 second, 1 second, and 1.5 second pulses from the frequency divider 7, and this constitutes the second selection circuit. 10 is a selection circuit 9
It is possible to count up to 3 million units using the pulse counting circuit from . Reference numeral 11 denotes a selection circuit for selecting either the output of the clock circuit 8 or the counting circuit 10, and this constitutes a first selection circuit. 12 is a decoder. Reference numeral 13 denotes a selection control circuit which selects either the output of the cycle selection switch or the million output of the counting circuit 10. 14 is a gate circuit.

Next, the operation will be explained. It is now assumed that the pulses from the selection circuit 9 in FIG. 2 are stopped by the start/stop switch 5 and counting is not performed. Further, the output of the clock circuit 8 is selected by the selection circuit 11 by the mode switch 3,
It is assumed that the time is displayed on the digital display section 1 as shown in FIG. At this time, the selection control circuit 13 selects the output of the period selection switch 4 based on the output of the mode switch 3. If 0.5 seconds is currently selected, the display section 2a will be displayed as shown in FIG.

Therefore, when the mode switch 3 switches to the counting display, the selection circuit 11 selects the counting circuit 10.
output is selected and its contents are displayed on digital display 1.
is displayed. On the other hand, if the selection control circuit 13 selects the 1,000,000th output of the counting circuit 10 based on the output of the mode switch 3, and if the 1,000,000th place is currently "1", then as shown in FIG. is displayed. In other words, in FIG. 4, the count value "1208623" is displayed.

Then, when the start/stop switch 5 is slid to the start side, the selection circuit 9 in FIG.
A pulse with a period of 0.5 seconds is generated and supplied to the counting circuit 10 for counting. If believers recite the daimoku at this counting speed, the number of daimoku times will be counted.

During this chanting, when the mode switch 3 is switched to the time display, the display section 2a switches to the counting cycle display and the gate circuit 14 displays the clock.
A pulse with a period of seconds is generated, and the display section 2a blinks with a period of one second as shown in FIG. Due to this, currently
It can be seen that chanting is being counted, and the cycle is 0.5 seconds.

In this way, chanting can be counted while the time is displayed, and the counting period can be known.

In addition, the blinking cycles of the display sections 2a to 2c are respectively
It may be set to 0.5, 1, or 1.5 seconds.

〔effect〕

According to the present invention, there is provided a display section that selectively digitally displays the time and count value, displays the counting cycle when displaying the time, and displays higher digits than the digital display section when displaying the count value. Therefore, when performing chant counting while the time is displayed, the counting cycle can be checked, and the counting display can be displayed up to the 1 million digit, which is the goal of believers, making it extremely easy to use.

[Brief explanation of the drawing]

Fig. 1 is a front view showing an embodiment of the present invention, Fig. 2 is a block diagram showing an example of the circuit configuration, and Fig. 3 is a front view showing an embodiment of the present invention.
5 are front views showing display modes in different usage states. 1 ...Digital display section, 2a-2c...Display section, 4...Period selection switch, 8...Time measurement circuit,
9... Second selection circuit, 10... Counting circuit, 11
...First selection circuit, 13...Selection control circuit.

Claims (1)

[Scope of Claim for Utility Model Registration] A clock circuit that measures time, a counting circuit that counts input pulses cumulatively, a mode switch that generates a selection output for selecting the above-mentioned time measurement circuit and the above-mentioned counting circuit; a first selection circuit that selects the output of either the clock circuit or the counting circuit according to the selection output of the mode switch; and displays the output selected by the first selection circuit; a second selection circuit that selects the period of the input pulse to the counting circuit based on the output of the period selection switch; and a second selection circuit that selects the period of the input pulse to the counting circuit based on the output of the period selection switch; a selection control circuit that selects an output of the counting circuit and selects an output of a digit higher than the most significant digit that can be displayed on the digital display section of the counting circuit according to a selection output of the counting circuit from the mode switch; , a display section that receives the output of the selection control circuit and displays the period of the input pulse or the output of a digit higher than the most significant digit that can be displayed on the digital display section of the counting circuit; clock.