JPS6246875B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides information that can be displayed on a display means by outputting at least one more position information for determining the position of information to be displayed than the number of information to be displayed. The present invention relates to a display device in which the brightness of the information to be displayed is kept substantially constant.

In conventional logic circuits, a large number of drive circuits are required to drive a multi-digit display, but a dynamic drive (described later) is generally used as a drive method to reduce the number of drive circuits. There is.

FIG. 1 is a diagram showing a circuit configuration for performing the dynamic drive.

In FIG. 1, information to be displayed is input from the left end of shift register 1, and control circuit 2
It moves to the right in the figure by the shift pulse output from. (Each arrow indicates the direction in which the information is transmitted). A portion of the output of the shift register 1 is returned from the right end of the shift register 1 to the left end of the shift register 1 through the signal line 1a. Therefore, the data stored in the shift register 1 is used repeatedly. The other part of the output of the shift register 1 is input to the decoder 3 one digit at a time from the right end of the shift register 1. The decoder 3 converts the input signal into information on a pattern to be displayed,
The converted signal is sent to the driver 4. The driver 4 drives the display 5 according to the input signal. On the other hand, other output pulses output from the control circuit 2 input a digit signal to the driver 6 for informing the number of digits of the signal output from the shift register 1. The driver 6 drives the display 5 according to the input signal. In this way, the display 5 is connected to the driver 4
The segment drive signal (signal of information to be displayed) output from the driver 6 and the digit drive signal (signal of position information) output from the driver 6 are driven in synchronization, and each digit is time-divided. indicate.
In recent years, with the spread of microcomputers, the control circuit 2 has been constructed of a microcomputer, and the microcomputerized control circuit has come to be controlled by a program. However, the shift register shown in FIG. 1 is generally expensive, and the program for driving the shift register is also extremely complicated.

The display device of the present invention eliminates the above-mentioned drawbacks, eliminates the need for the shift register, simplifies programming, and maintains constant brightness of the display.

The present invention will be explained below with reference to the drawings.

FIG. 2a shows a circuit block diagram of the display device of the present invention, and the shift register 1 and control circuit 2 in FIG. 1 are shown by broken lines and can be replaced with the control circuit 7. Then, the control circuit 7 operates the decoder 3', segment driver 4' (display information output means), and digit driver 6' (position information output means) to display information to be displayed on the display 5' (display means). have them do it. When the information to be displayed on the display 5' is, for example, a number, it can be displayed by lighting a predetermined segment among seven segments 5a to 5g made of LEDs (light emitting diodes) as shown in FIG. 3a. It can be displayed.
When the numerical data to be displayed is a five-digit decimal number, a display device 5' is obtained by arranging the display sections 19 to 23 in parallel as shown in FIG. 3B. The input section of the decoder 3' is connected to each output section Q of the buffer registers 16e to 16h in the control circuit 7,
The input section of the digit driver 6' is connected to the control circuit 7.
It is connected to each output section of the decoder 3a at. The input section of the decoder 3a is the buffer register 1.
It is connected to each output section Q of 6a to 16c. Each data input section D of the buffer registers 16a to 16h can receive data processed by the CPU 8 through the data bus 12. CPU8 is 8
A BIT microcomputer M6800 made by Motorola and configured as shown in FIG. 2b can be used.

In FIGS. 2a and 2b, the input section of the clock signal generator 9 and the AND gate 15 is connected to the signal line 17.
The signal line 18 has an input part of an AND gate 15, and the data bus 12 has a RAM (Random Access
Memory) 10, ROM (Read Only Memory)
11, buffer registers 16a to 16h are connected to the Andres bus 13 and an Andres decoder 14, respectively. The ROM 11 stores control programs, and the RAM 10 is used as registers necessary for data processing. The RAM 10 and ROM 11 perform predetermined operations under the control of the CPU 8. On the other hand, the timing input portions T of the buffer registers 16a to 16h are connected to the input portions of the AND gate 15 which input the output signals of the AND gate 15 [pulse signals P1 to P6 shown in FIG. 4f]. An output signal from the address decoder 14 to detect addresses 16a to 16h, an output signal from the CPU 8 via a signal line 18 to instruct writing or reading,
A signal from a clock signal generator 9 via a signal line 17 is applied to output a signal from the output of the AND gate 15 at a predetermined time interval.
Andres decoder 14 receives an output signal from CPU 8 via Andres bus 13.

In the above configuration, when a five-digit display as shown in FIG. 3b is driven by the dynamic drive, the input signal waveforms of the display sections 19 to 23 shown in FIG. It will look like Figure 4 a to e. (Here, the horizontal axis represents time, and the vertical axis represents voltage or current). That is, the digit signal 19 in FIG.
a, 19b... to display the display section 19 in FIG.
Figure 3b is determined by the digit signals 20a, 20b... in Figure b.
is displayed on the display section 20 (in other words, it is displayed at the 2-digit position), and the same goes for the rest. In FIGS. 4a to 4e, T _A and T _B represent the driving time of the display 5', while in FIG. 4 e, the time T _B (>
During T _A ), that is, while the CPU 8 is controlling, the display section 23 continues to be driven, so only the display on the display section 23 becomes particularly bright.

This is to operate decoder 3' and decoder 3a in FIG. 2a for five digits each (the same number).

In the display device of the present invention, five digits of information to be displayed are input to the decoder 3', and the decoder 3'
A digit signal for six digits (that is, a signal that is one digit more than the input to the decoder 3') is input to a. As a result, in the display device of the present invention, the display section 23 can be changed to another display as shown by the broken line 23a' in FIG. 4e by the pulse signal of the 6th digit shown by the broken line P6 in FIG. Similarly to parts 19 to 22, it can be driven for a time T _A . (Note that the time during which the CPU 8 is performing control can be expressed as T _B or T _{B −TA} ).

First, in order to display the number pattern shown in FIG. 3b, "1" is entered into the 8-bit accumulator B, 8b in FIGS. 2a and 2b.

() 16-bit index register 8d n
Enter (address designation).

() Input data (information to be displayed) into the accumulators A and 8a from the address pointed to by the index register 8d (that is, address #n of RAM 10 at first).

() Add the accumulator A, 8a and the accumulator B, 8b, and put the added value into the accumulator A, 8a.

() Put the contents of the accumulators A and 8a into the buffer registers 16a to 16h (FIG. 2a).

() The contents of accumulator B and 8b are changed to 5 by ALU (Arithmetic Logic Unit) 8c.
(digit) or less, and if it is less than or equal to 5, add 1 to accumulator B, 8b, then add 1 to index register 8d, and then ()
~ Follow the steps in (). Here, normally, if the number of digits displayed on the display is 5, the AND gate 1
The output signal No. 5 is composed of P1 to P5 shown in FIG. When the pulse signal P6 is output, the waveform indicated by the solid line 23a in FIG. 4e changes to the waveform indicated by the broken line 23'a. Therefore, all of the display sections 19 to 23 shown in _FIG . It can be kept almost constant. Further, since the display device of the present invention does not use a shift register as described above, the circuit is simplified, and the program for operating the control circuit 7 may be simple.

[Brief explanation of the drawing]

Fig. 1 is a circuit block diagram of a conventional display device, Fig. 2a is a circuit block diagram of a display device of the present invention, Fig. 2b is an internal circuit configuration diagram of the CPU shown in Fig. 2a, and Fig. 3 Fig. 3a is a plan view showing a 7-segment display section, Fig. 3b is a plan view when the display section is arranged in 5 digits, Figs. Figure f is a waveform diagram of the pulse signal output from the AND gate.
g...segment, 6,6'...digit driver, 7
...Control circuit, 8...CPU, 9...Clock signal generator, 10...RAM, 11...
ROM, 14... Andres decoder, 15...
AND gates, 16a-16h... buffer registers, 19-23... display section.

Claims (1)

[Claims] 1 It does not have a display information output means for outputting information to be displayed, a position information output means for outputting position information for determining the position of the information to be displayed, and a shift function for storing the display information and the display position information. a storage means, and a display means for displaying the information to be displayed at a predetermined position according to the output of the storage means, and the storage means stores at least one more number of the position information than the number of the information to be displayed. A display device characterized in that the brightness of the information to be displayed displayed on the display means is made substantially constant at each position by outputting the information from the display means.