JPH03217897A - Circuit for crt display - Google Patents

Abstract

PURPOSE:To reduce chip area by storing a line feed code and a continuous display OFF code in a 1st memory in addition to character codes. CONSTITUTION:A continuous non-display code of data in the 1st memory 21 is detected by a continuous display OFF code detecting circuit 23 to put a continuous display OFF control circuit 24 in operation, a display stop signal 13 is sent to a CRT display output circuit 33 on the code detection to load non-display character quantity data in the continuous display OFF code in a down counter 25, and further an address increment stop symbol 36 is sent to a memory control circuit 31. The counter 25 counts down from the loaded initial value with a character count signal 37 generated by a timing generating circuit part 30 with each dot clock signal 8 of one character and when the counter reaches 0, the circuit 24 resets the address increment stop signal 36 and signal 13 to restart normal display operation and continue the display operation until a line feed code detecting circuit 26 detects the line feed code. Consequently, the chip area is reducible.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a CRT display circuit for displaying characters such as numbers and letters on a CRT screen.

2. Description of the Related Art Conventionally, a CRT display circuit for displaying characters on a CRT screen, as shown in the block diagram of FIG.
a first memory 2 that stores the character shape, a second memory 3 that stores the shape of the character addressed by the output of the first memory 2, and a CRT that stores the output data of the second memory 3.
A shift register 4 for converting data into display data, a CRT display output circuit 5, a horizontal synchronizing signal 6, a vertical synchronizing signal 7 and a dot clock 8 are used to control the first and second memories 2, 3 and the shift register 4. A timing generation circuit that generates a timing signal to be applied to the resistor 4 and the CRT display output circuit 5, and character codes stored in the first memory 2 that are predetermined as codes for turning off the display on the screen. The display OFF control circuit 10 turns off the display by one character when a code is detected.

Problems to be Solved by the Invention However, according to this configuration, the code for turning off the display is stored in the first memory 2 that stores the types of characters.・Because it is stored as one of the codes, one character is displayed on the screen per display memory address.
By simply specifying FF, for example, when displaying a line divided into the left end and right end on the screen as shown in Figure 4,
In the non-display section between the two, it is necessary to store display OFF codes in the first memory 2 for the number of non-displayed characters, and as a result, the first memory address is wasted. In particular, random access memory (hereinafter referred to as RAM) is often used as the first memory 2 due to the need to rewrite display contents, but due to its structure, RAM is more difficult than read-only memory (hereinafter referred to as ROM). Since the area per bit is extremely large, several times larger, a display like the example in Figure 4 requires a much larger memory capacity than the number of characters to be displayed, and if the CRT display circuit is integrated, the chip - There was a problem of increased size.

Means for Solving the Problems The CRT display circuit of the present invention solves the above-mentioned problems, and stores screen control data such as the type and position of characters to be displayed, and the size of characters to be displayed. A first memory and a second memory that stores the shape of the character.
, a control circuit for controlling these memories, a shift register for converting the output data of the second memory into CRT display data, a display output circuit, and a display sandwiched between characters on the screen. A continuous display OFF control circuit unit realizes a non-display interval with data for one address in the first memory, and detects the line feed code stored in the first memory address corresponding to the end of each line, and detects the line feed code stored in the first memory address corresponding to the end of each line. A line feed control circuit section that sets the display position, size, and first memory read address at the beginning of the line, and further includes a horizontal synchronization signal, a vertical synchronization signal, and a dot clock.
, second data memory and shift register, CR
A timing generation circuit generates a timing signal to be applied to a T display output circuit.

According to the present invention, instead of storing a display OFF code for one character per address of the first memory as in the conventional case, by storing a continuous display OFF code for turning off the display for an arbitrary number of characters. Since it is possible to continuously display no display for multiple characters in one line of display using one word of data in the first memory, it is possible to reduce the capacity of the first data memory required to perform the same display. Since rewriting is generally required, it is possible to reduce the capacity of RAM used as the first memory, and the area occupied by RAM, which has a large area per bit on large-scale integrated circuits, can be reduced, so the chip area of large-scale integrated circuits can be reduced. It becomes possible to reduce the size.

In addition, the line feed control circuit allows the number of characters included in a displayed line on the screen to be set arbitrarily, making it possible to display more lines using the same capacity of the first data memory. The degree of freedom in display increases.

Embodiment An embodiment of a CRT display circuit according to the present invention will be described with reference to the functional block diagram shown in FIG. This circuit is the interface circuit 2 with the control microcomputer.
0, the first memory 21, the second memory 22, the continuous display OFF code detection circuit 23, and the continuous display OFFil.
l control circuit 24, down counter 25, line feed code detection circuit 26, line feed control circuit 27, register 28, one line display end signal generation circuit 29, timing generation circuit 30, memory control circuit 31, , shift register 3
2 and a CRT display output circuit 33. The first memory 21 has a dot clock signal 8, a horizontal synchronization signal 6,
This is a memory that is accessed by a read address output from the memory control circuit 31 that receives a timing signal generated by the timing generation circuit 30 from the vertical synchronization signal 7, and is designated by "A".
A code indicating the type of character such as "B", a line feed code including the display start position and size of the next line, the first memory read address at the beginning of the line, and a continuous non-display code that specifies continuous non-display over multiple characters. This is made up of RAM.These data access the second memory 22.The second memory 22 is a memory that stores the shape of the character.Second memory 22
The output is input to a shift register 32 for converting it into time-series CRT display data, and is further displayed on the screen via a CRT display output circuit 13 which converts the data from the shift register 32 into a CRT display signal 14. be done. However, if a continuous display OFF code and a new line code are detected, shift register inhibition signals 34 and 35 inhibit output from the shift register 32. Among the data in the first memory 21, the continuous non-display code is continuous display OFF.
It is detected by the code detection circuit 23, and the continuous display OFF control circuit 24 is operated. Upon detection of the code, the continuous display OFF control circuit 24 generates a display stop signal 13 to the CRT display output circuit 33, loads the non-display character number data included in the continuous display OFF code into the down counter 25, and further loads the data into the memory. For the control circuit 31, the address
An increment stop signal 36 is generated. The down counter 25 counts down from the loaded initial value using the character count signal 37 generated by the timing generation circuit section 30 every 8 dot clock signals for one character, and when the value reaches O, The continuous display OFF control circuit 24 cancels the address increment stop signal 36 and the display stop signal 13, resumes normal display, and continues displaying until the line feed code detection circuit 26 detects a line feed code indicating the end of a line. When a line feed code is detected, the line feed control circuit 27 determines the display start position of the next line included in this address,
The size and the first memory read address of the beginning of the line are stored in the register 28, and the one line display end signal generation circuit 2
9 outputs a one-line display end signal 38 to the outside at a timing on the last horizontal scanning line constituting the currently displayed line. Furthermore, with reference to FIG. 2, the principle of display on a CRT screen will be specifically explained. Note that FIG. 2 is an example of the CRT display of FIG. 1, and the first memory 21 is assumed to be a 16-word RAM at addresses 0-F. Addresses O-3, Addresses 5, Addresses 7-8 of the first memory 21
street address. Character codes are stored at addresses A to E, and characters corresponding to each code are displayed on the screen. Furthermore, line feed codes are stored at address 4, address 9, and address F of the first memory 21. Furthermore, at address 6, there is a continuous display OFF code and data “6” indicating the number of non-display characters.
” is remembered.

Among the data in the first memory 21 that is accessed by the read address generated by the memory control circuit 31 that receives the timing signal output from the timing generation circuit 30 from the vertical synchronization signal 7, horizontal synchronization signal 6, and dot clock signal 8. The character codes at addresses 0 to 3 access the second memory 22, and the output of the second memory 22 is converted into time-series data by the shift register 32, and then displayed on the screen by the CRT display output circuit 33. will be displayed data. When the data (line feed code) at address 4 of the first memory 21 is accessed, the display of this line is ended and the data included in the line feed code is transferred to the display start position, size, and number of the beginning of the next display line. It is stored in the register 28 as a memory read address of 1. Through the above operations, the four characters in the first line of display are displayed on the screen. Further, after the first line display is completed, a one line display end signal 38 is outputted to the outside. The second display line starts displaying from the display position determined by the line feed code of the first line, and
Display starts from address 5, which is the first memory read address at the beginning of the second line specified by the line feed code of the line, and the character specified by the character code of address 5 is displayed in the first line. Display as shown. Next, address No. 6 is accessed and continuous display O
When the FF code is detected, the value “6” is the number of non-display characters.
is loaded into the down counter 25 as an initial value.

Down counter 25 receives character count signal 37
The continuous display OFF control circuit 24 keeps the display OFF until the value of the down counter 25 reaches "O" and stops incrementing the RAM read address. When the value of the down counter 25 becomes "O", the RAM read address is incremented, address 7 is accessed, and normal display operation is resumed. When address No. 9 is accessed and a line feed code is detected, a line feed operation similar to that for the first line is executed, and a one line display completion signal 38 is output to the outside.

While the display of the third row is being executed according to the same principle as above, the external controller sends the address O of the first memory 21, which has been completely displayed, through the interface circuit 20 at the timing of the one-row display completion signal 38. The data at addresses 9 to 9 is rewritten to prepare for display on the fourth line on the screen.

When the display of the third line is completed, the first memory 21 that was rewritten during the display of the third line is sequentially used for display within the same screen field, and the display of the fourth line and subsequent lines becomes possible. .

Effects of the Invention As described above, according to the present invention, in addition to character codes, the first memory stores line feed codes and continuous display OFF codes, which causes problems when displaying a large number of characters on the screen. The increase in RAM capacity can be suppressed to the necessary minimum. As a result, when integrated,
Chip area can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a CRT display circuit according to the present invention, FIG. 2 is a diagram showing an example of a screen display according to the present invention and its display principle, and FIG. 3 is a block diagram showing a conventional CRT display circuit. FIG. 4 is a diagram showing the correspondence between the display on the screen and the data memory address for storing display data for one screen according to the conventional example. 1... Control data, 2, 21... First
memory, 3, 22... second memory, 4, 3
2...Shift register, 5, 33...
・CRT display output circuit, 9, 30...timing generation circuit, 10...display OFF control circuit,
11.31...Memory control circuit, 14...
...CRT display signal, 23...Continuous display OFF
Code detection circuit, 24... Continuous display OFF control circuit, 25... Down counter, 26...
...Line feed code detection circuit, 27...Line feed system m
Circuit, 28...Register, 29...1
Line display end signal generation circuit.

Claims (1)

[Claims] a first memory for storing on-screen display data and screen control data; a second memory for storing character shapes (fonts) addressed by character codes among the data in the first memory; A data memory section consisting of a control circuit that controls first and second memories, and a CRT that transmits data output from the data memory section.
identifying a continuous display OFF code from among the data in the output circuit section and the first memory to output as display data;
a continuous display OFF control circuit unit that erases the display on the screen by the number of characters included in the continuous display OFF code;
a line feed control circuit unit that detects a line feed code stored in a first memory address corresponding to the end of each line and sets the display position and size of the next line and a first memory read address at the beginning of the line; - A CRT display circuit comprising a memory section, the output circuit section, the continuous display OFF control circuit section, and a timing generation circuit section that generates a timing signal to be applied to the line feed control circuit section.