JPS6246495A - Eeprom device - Google Patents

Abstract

PURPOSE:To highly integrate a memory array by constituting a peripheral circuit of a CMOS circuit, supplying an earth potential/power source voltage to a common source line of the memory array and short-circuiting a word line and the common source line during reading. CONSTITUTION:A matrix like memory cell of a memory array M-ARY consists of a separating Q3 between sources of address selecting Q1, Q2 between a drain of a MOSFET Q2 and a data line D1 and a common source line CS. A semiconductor area WELL in which the M-ARY is formed is erlectrically separated from a semiconductor area in which an N-MOSFET constituting a peripheral circuit of an X decoder, a Y decoder or the like is formed. During a reading operation, an earth potential of a circuit is applied to the line CS through Q7, Q8 and even when the electric potential of the line CS is raised by threshold voltage of the Q7, Q8, electric potentials of word lines W12, 22 are equal according thereto.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to an EEPROM (Electrically Erasable Programmable Read-Only) device, in which, for example, a peripheral circuit thereof is constituted by a CMO5 (complementary MO5) circuit. It relates to techniques that can be effectively applied to things that have been developed.

[Background technology]

MNOS (metal nitride oxide semiconductor) is an insulator that has a gate insulating film with a two-layer structure: a relatively thin silicon oxide film (oxide) and a relatively thick silicon nitride film (nitride) formed on top of it. A gate field effect transistor (hereinafter simply referred to as an MNOS transistor or simply MNOS) is capable of electrically writing and erasing stored information. type source and drain regions are formed;
A gate electrode made of N-type polycrystalline silicon is formed on the surface of the P-type silicon region between the drain regions through a gate insulating film made of, for example, a 20-thick silicon oxide film and a 500-thick silicon nitride film. It is formed. The P-type silicon region constitutes the substrate gate region of the MNOS.

In an erased state or a state in which no memory information is written, the gate voltage vs. drain current characteristic of the MNOS is such that the threshold voltage is a negative voltage.

In order to write or erase stored information, a high electric field is applied to the gate insulating film so that carriers are injected or released due to a tunneling phenomenon.

In the write operation, the substrate gate is applied with, for example, a ground potential of 0.times., and a high voltage of, for example, +15V is applied to the gate.

Depending on the information to be written, a low voltage of x' o v or a high voltage such as +12V is applied to the source and drain regions.

Silicon between source and drain regions
A channel is induced on the surface of the gate region in response to the high positive voltage applied to the gate. Potential of this channel
1 is equal to the potential of the source and drain regions. When a voltage of Ov is applied to the source region and the drain region as described above, a high electric field corresponding to the high voltage of the gate acts on the gate insulating film. As a result, electrons as carriers are injected from the channel into the gate insulating film due to a tunneling phenomenon.

As a result, the threshold voltage of the MNOS changes from, for example, a negative voltage to a positive voltage.

When +12V is applied to the source and drain regions as described above, the potential difference between the gate and the channel is reduced to several square meters. Such a low voltage difference is insufficient to cause electron injection by tunneling. Therefore, the threshold voltage of MNOS does not change.

In addition, in the case of erasing, a high voltage such as +15V is applied to the substrate gate while applying Ov to the gate, causing a tunnel phenomenon in the opposite direction, and electrons as carriers are returned to the substrate gate. .

The substrate gate is, for example, a P-type well region formed on an N-type semiconductor substrate. Therefore, the N-type semiconductor substrate is changed in accordance with the potential change in order to maintain a reverse bias state with respect to the well region. Therefore, EEFROM that performs such write/erase operations
In this case, its peripheral circuitry is comprised only of N-channel MOSFETs formed in other P-type well regions to which high voltage is not applied even during writing. Because 0
In order to make the M03 circuit, P
It is necessary to form a channel MOS FET. In this case, when the substrate is brought to a high potential such as +15V in accordance with the change in the well potential as described above, the P-channel MOS FET formed there will be affected by the substrate effect caused by the high voltage. threshold voltage increases to normal signal levels (e.g. 0 to +5V).
) would make it inoperable.

Therefore, the inventor of the present application has developed an approach to reduce the MN by using a relatively low power supply voltage such as +5V and a negative high voltage.
We considered writing and erasing data by relatively changing the voltage difference between the OS gate and the substrate gate. As a result, the potential of the semiconductor substrate can be fixed at a relatively low potential such as about +5V, so that the P
Channel MOSFETs operate with normal signal levels. As a result, the peripheral circuitry can be configured with 0M03 circuits, so that lower power consumption and higher speed operation can be achieved.

In addition, the inventor of this application has installed an isolation MOS in the source of the MNOS.
We considered providing a FET and connecting it to a common source line to couple the sources of the MNOS and omitting the reference potential line running parallel to the data line. In this case, the switch for controlling the potential of the common source line (connecting the common source line to the reference potential) using the normal signal level is an N-channel MOSFET that is turned on by the negative potential on the common source line. Therefore, a P-channel MOS FET must be used. However, when a P-channel MOSFET is used, the potential of the common source line rises to a level higher than the ground potential of the circuit due to its threshold voltage.
As the source potential of the MNOS rises during a read operation, its effective threshold voltage is increased, and there is a risk that the MNOS transistor, which is designed to have a negative threshold voltage, may become inoperable. . For the MNOS technology, see, for example, Japanese Patent Laid-Open No. 156370/1983.

[Purpose of the invention]

An object of the present invention is to provide an EEPROM device in which the peripheral circuitry is CMO3 circuitized and the memory array is highly integrated.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the peripheral circuit is configured with a CMOS circuit, and an isolation MOS FET is connected to a common source line in a memory array in which memory cells including MNO3I-transistors are arranged in a matrix and connected to a common source line via an isolation MOSFET. MOS of opposite conductivity type
In addition to supplying the ground potential/power supply voltage of the circuit through FET, the above MNO3I-
The gate of the transistor shorts the coupled word line and the common source wire.

〔Example〕

FIG. 1 shows a circuit diagram of a main part of an embodiment of the present invention.

The EEPROrν1 device of this embodiment includes an address selection circuit consisting of an address decoder, an and a control circuit to form the control signal. The figure shows a memory array M-ARY and its selection circuit. The X address decoder X-DCR and the like forming the selection circuit are formed of CMOS circuits. The CMOS circuit operates by being supplied with a low power supply voltage of +5V. Therefore, the level of the selection/non-selection signal formed by address decoders X-DCR and Y-DCR is -+5y,
The low level is set to OV, which is the ground potential of the circuit.

A high negative voltage -vpp is used for write/erase operations on the MNO3I-transistor.

This voltage (-VPI) is approximately -12V, and in addition to being supplied from an external terminal, it is also formed by a level conversion circuit that rectifies the pulse signal formed by the oscillation circuit that operates at +5V to form a negative voltage. It may be something that does.

In FIG. 1, a memory array M-API includes memory cells arranged in a matrix.

The memory cells are MN, as exemplarily shown.
lFj between the drain of the OS transistor Q2 and the data source (bit line or digit line) DI
An isolation MOSFET Q3 provided between the source of the S transistor Q2 and the common nozzle spring C3.
It consists of

Gate number of MOS FETQ 1 for address selection of each memory cell arranged in the same row, 1st
M commonly connected to word line Wll and corresponding to Qll
The gates 1 of the NOS transistor Q2, etc. are both connected to the second word line W12 by 3M. Same) Memo IJ7 address selection MOS F placed on the same line
ET and MNO5I-Landisk's Kate, 'c'F' hf411 '7-f' line W21. Commonly connected to W22.

A! of memory cells arranged in the same column! ! The drains of the response j51 selection MOSFET Q1 and the like are commonly connected to the data line DI. Similarly, the drains of the address selection MOSFETs of other memory cells arranged in the same column are commonly connected to the data line D2.

According to this embodiment, the MNOS transistor is
Since the configuration is such that the storage information of the OS is erased, the base gate, that is, the semiconductor region WELL in which the memory array MARY is formed, has an N-channel MOSFET that constitutes peripheral circuits such as an X decoder and a Y decoder. It is electrically separated from the semiconductor region (well region) to be formed. As will be described later, the well region WELL in which the memory array MARY is formed is composed of, for example, a P-type well region formed on the surface of an N-type semiconductor substrate.

A power supply voltage Vcc of ↓5V is constantly supplied to the N-type semiconductor substrate.

For the above-mentioned erasure, individual memory cells can be formed in independent well regions, or memory cells arranged in the same row or column can be formed in a common well region. In this case, the entire memory cells, ie, the memory array M-ARY, are formed in one common well region WELL.

Said first two-d line Wl 1. W21 is X
NOR gate circuit N0RI that constitutes a decoder
, N0R2 is coupled to an output terminal of a gate circuit G, which will be described later, which selectively transmits the output signals of N0R2. The word lines wtz and w22 of ff12 are connected to the NOR gate circuit N, respectively.
Selectively about -1 according to the output signals of 0R1 and N0R2
Level conversion circuit LV that outputs a negative high voltage such as 2V
It is coupled to the output terminal of C. In addition, separation MOS F
The gates of ETQ3 etc. are shared, and the control voltage generation circuit V
A control voltage Vig formed by ig-G is supplied. The source of these separation MOS FETQ 3 etc. is
Each of them is shared to form a common source line C8, and a parallel type P-channel MO8FETQ? , Q8 and the P-channel MOS FET Q6 are selectively supplied with the circuit ground potential or power supply voltage VCC. According to this embodiment, the data line is brought to a negative high potential during the write/erase operation. Therefore, its source potential is set to a negative potential, and the signal (OV.

Switch MOSF that performs on/off operation by 5V)
A P-channel MO8FET is inevitably used as the ET. Above MOSFETQ7. The control signal er is supplied to the gate of MOSFET Q6, and the control signal or is supplied to the gate of MOSFET Q6. ■It is inverted and supplied by. As a result, the above MOSFET Q?
, QB and Q6 are turned on/off in a complementary manner depending on the level of the control signal ar. Further, a second word line W12 to which the gate of the MNOS transistor is coupled
．． A P-channel switch MOS that receives the control signal er/we is connected between the W22 etc. and the shared source line.
FETQ4. Q5 etc. will be provided. These switches M
OSFETQ4゜Q5 is turned off by setting the control signal er/we to high level during erase and write operations, and is turned off during read operations.
1 and 6", the #' state is established. 6. As a result, during the readout operation, the gate voltage of the second word line, in other words, the gate voltage of the MNOS transistor 1 is equal to its source voltage. is made equal to
1□ This allows the P channel to be
171zMOSFETQ? ,Q8GsukeLi'A
Pass 7-X1! 'When the ground potential of the circuit is applied to C3, the potential of the common source line CS is Q7. Q8
The potential of the second word line 1 is equally 7□, even if it is raised by the threshold voltage of 3, 1-1, for example -. , : an MNOS transistor with a negative threshold voltage such as 5v can be kept in the on state.

t tt b 9・Ai [l17- Z * CS (
7) 478 l-, “9°1゛.

This results in an increase in the effective threshold voltage due to the substrate effect of the N03 transistor.
This is because if the threshold voltage is as small as -0.5V as in No. 1, the memory current that should selectively flow will no longer flow.

As described above, the sources of the MNOS transistor Q2 and the like are shared through the isolation MOSFET Q3 and the like. As a result, the MNOS transistor and the address selection MOS F
Since the source line (reference potential line) running parallel to the data line is not required as in the case of using a memory cell consisting of an ET, the memory array can be highly integrated.

The above-mentioned isolation MOSFET Q3 etc. are connected to the first and second word lines Wll, 12 of the selected memory cell in the MNOS transistor operation as described later.
etc. are set to high level (5■), the well region WELL as the base gate is set to about -12V, and the data line D1 is set to about -10V, the control voltage Vi
It is turned off by bringing g to a low potential, such as about -0.0V. This prevents current from flowing from the high level (approximately 5 V) of the data line D2, which is set to be unselected (IF writing is blocked), to the memory cell to which writing is to be performed.

Well region W where the memory array M-ARY is formed
A control voltage Vw generated by a control voltage generation circuit Vw-G is supplied to ELL. This voltage Vw is set to a negative high voltage of about -12V during a write operation,
During the erase operation, the potential is set to approximately +SV.

Each data number of memory array M-ARY! J:D1. D2
A switch as a Y gate circuit is connected between the common data and the common data CD.
0 etc. can be set. these? /fO5FETQ9. Q
At the gate of IO, there is a Y tick 1-da Y-DC (not shown).
An output signal of R is provided. The above common data line CD is
Input/output circuit 10B-t - The input terminal of the data input circuit and the output of the data output circuit that constitute this input/output circuit I CI B are connected to the output terminal of the data input circuit and the input terminal of the data output circuit. A is external terminal I
10.

Although not particularly limited, each data iit, Dz, etc. is provided with a level conversion circuit LVC that changes the voltage to a negative high voltage -Vpp according to the level of the selected data line for the insertion operation. It will be done.

FIG. 2 shows a circuit diagram of an embodiment of a gate circuit G and a level conversion circuit LVC that constitute a unit circuit of the X-decoder X-DCR.

The gate circuit G includes an N-channel MOSFET Q11 that transmits the output signal of the NOR gate circuit N0RI to the first word line Wll in accordance with the control signal Maτ', and a control signal we'' having an opposite phase to the control signal Maτ°. N-channel MOSF that provides the circuit ground potential to word line W11 of No. 1
Consists of ETQ12. That is, during the write operation, the transmission gate MOSFET QI1 is turned off by the low level of the control signal MAT', and the MOSFET QI2 is turned on by the high level of the control signal we', so that the first word line W1L etc. All of them are set to the ground potential of the circuit. During an erase or read operation, the first word line Wil is set to the above control a (No. 8 ma τ″
Transmission game by the high level of , the low level of we'')
MOSFETQll and the like are turned on and set to high and low levels according to the output signal of the NOR gate circuit NOR1. That is, the word line Wll is set to a high level (5■) if it is in a selected state, and is set to a low level (OV) if it is in a non-selected state.

Level conversion circuit LVC is MOSFETQI3~Q19
and an inverter circuit IVI.

The output terminal of the NOR gate circuit N0RI is the control signal w
P-channel type transmission gate MOSFET receiving ets
It is coupled through QI 3 to the second word line W12.

Also, the NOR gate circuit N mentioned above.

The output terminal of the inverter circuit 11 which receives the output signal of R1 is connected to the second word line W via the P-channel type transmission gate MOSFET QI4 which receives the control signal ert.
12. The second word line W12 is selectively brought to a negative high voltage (-VPI) by the next level conversion circuit according to its level. The circuit for selectively applying the negative high voltage -vpp to the word line W12 is composed of the following circuit elements. Although not particularly limited, between the second word line W12 and the negative voltage terminal -vpp, there is a diode-type P-channel MOSFET that allows current to flow from the negative voltage -VPP toward the word line W12.
Q15 is provided. Between the negative voltage terminal -Vl)P and one electrode of the capacitor C is a P-channel MOSFE whose gate is connected to the second word line W12 side.
TQ16 is provided.

One electrode of the capacitor C and the second word line W
12 is a diode-type P-channel MOSFET QI 7 that allows current to flow from the word line side.
is provided. The other electrode of the capacitor C has a gate connected to the second word line WlZ side.
An oscillation pulse generated by an oscillation circuit O8C (not shown) is supplied through the channel MOSFET Q1B. Furthermore, the ground potential of the circuit is applied to the word line W12 by the P-channel MOSFET QI 9, which receives seven control signals, before the level conversion circuit starts the level conversion operation.

The level conversion operation of this embodiment is as follows.

For example, during an erase operation, the control signal cr is first temporarily set to a low level, and the second word line W12 is reset to the ground potential of the circuit. After this, the control signal art is set to low level. This allows MOSFETQI
4 is turned on.

For example, high level selection 1 from NOR gate circuit N0RI
Signal 7゛Sending kl''6・9''''-evening circuit 1
□: A low level signal is sent to the above MO3 via v1.
FE 1TQ14 will be informed,
As a result of having the gate and source of the MOSFETQ j14 at the same potential, the MOSFETQ j14
is turned off. This 1. causes the second word line W12 to be in a floating state.
□・Maintain the above low level in the state. 2nd above
When word IJjW12 is set to low level in a floating state, when the oscillation pulse is set to high level, MooFETQ"°""74.i@'"
8 hT −4” −p′<1: Precharge the capacitor C. Next, the above oscillation bar:
.

When the pulse is brought to the ground potential of the circuit, the capacitor C forms a negative potential due to the bootstrapping effect. MOSFETs Q17 and Ql6 are turned on by this negative potential, and the potential of the second word line is lowered by the negative voltage due to the bootstrap effect by the negative voltage -Vl)P. Next, when the oscillation pulse is brought to a high level, the capacitor C is precharged to a level as large as the negative voltage, so by repeating the same operation, the negative voltage -VpI) becomes negative, such as about 12V. If the voltage is high, the potential of the second word line W12 is lowered to a low potential such as about -10V. Note that the diode type MOSFETQI
7. Since there is a threshold voltage of Ql 6, even if the negative voltage VPP is -12V as described above, the potential of the word line W12 only decreases to a potential of -10V. On the other hand, if a low-level non-selection signal is sent from the NOR gate circuit N0R1, a high-level signal is transmitted to the MOS FET Q14 via the inverter circuit IVI, so the potential of the second word line W12 is It is set to a high level of about 5■.

In the write operation, the control signal τ lower is temporarily set to a low level, and after the second word line W12 is reset to the ground potential of the circuit, the control signal wets is set to a low level. This turns on MOSFET Q13. For example, a high level selection signal from the NOR gate circuit N0RI 11':1%l>'! ! 5
8 FLf= fL, 612? M*M('iE h I
, 0°, :゛i 1゜2 The potential of the word line 12 is at a high level such as approximately 5■ 1゜1' If a low level non-selection signal is sent to the word line 12,
11'1: The potential of the second word line W12 is set by the level conversion circuit described above.
1:1・LVC operates and becomes -10V.
:1 The third figure is 12,1. A, I M-ARY
A circuit diagram of an embodiment of the control voltage generation circuit V w -G II for the well WELL, which is formed, is formed, and is connected to the well WELL is shown.

This circuit receives the control signal erts and performs an erase operation.
□O between P channels to output +5v during operation
81□ FET°′°′″1!ia4#('f4)”CilJ
□(l 1”4ゞktl-ihc, t' y4
Jeficf, (IQ'y“tv@:.

P-channel MO to be reset to the ground potential of the circuit
It is constituted by SFETQ21 and a level conversion circuit LVC similar to the above-mentioned 1 which receives a low level (ground potential) in a floating state and lowers it to a negative voltage -vpp such as -112. Note that the oscillation pulse OSC required for the level conversion operation is supplied via a P-channel type transmission gate MOSFET Q22 that receives the write control signal 7τ°.

Note that the control voltage generation circuit Vig-G forms the control voltage Vig supplied to the gates of the isolation MOSFET Q3, etc.
The circuit is also constructed of a circuit similar to that shown in FIG. 3 above, except that the control signals are different. Further, the level conversion circuit LVC provided on the data line is constituted by a circuit similar to that shown in FIG. 2 above. However, it goes without saying that the level conversion circuit operates according to the write signal level of the selected data line rather than the output signal of the address decoder.

In the erase operation, the well region WELL is set to +5V and the second word line is set to 110V, so that the electrons in the floating gate are returned to the base gate side. Also,
In a write operation, the MNOS to which the write is performed
The second word line to which the gate of the transistor is coupled is +5
In (2), the well region WELL is set to -12V, its data line corresponding to logic "1" is set to -10V, and the data line corresponding to logic "0° (write inhibit) is set to +5V.
It is made into V.

Note that in the read operation, the data line selected by the Y gate is coupled to the input terminal of the sense amplifier included in the data output circuit. The sense amplifier reads stored information by sensing current flowing through a memory cell coupled to a selected data line and word line.

〔effect〕

(llMNOSt- In a memory cell in which an isolation MOS FET is provided between the source of the transistor and a common source line, a readout By providing a shorted MOS FET that is turned on during operation, the gate and source of the MNO3I-transistor can be made equal.This allows the MNOS transistor to follow its threshold voltage regardless of the floating of the common source line. This provides the effect of allowing current to flow.

+21MN03I-MOS for separating the transistor source
By sharing them via FET, the reference potential line running parallel to the data line of the memory array can be omitted.
The effect of realizing a high S product of the memory array can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. A latch circuit is provided on the data line to transfer the storage information of all memory cells of the selected word line prior to the write operation, and
The latch circuit corresponding to the memory cell to be written may be rewritten, and the entire erasing for the word line and the write operation according to the information held in the launch circuit may be performed continuously. Further, the specific circuit configuration of the level conversion circuit that selectively generates a negative high voltage using the X decoder, the latch circuit, and the control signal may be of any type.

[Application field]

This invention consists of 1. It can be widely used as an EEFROM device.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the main part of an EEPROM device according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of the X decoder and level conversion circuit, and FIG. FIG. 2 is a circuit diagram showing an example of a supplied control voltage generation circuit. M-ARY...memory array, X-DCR...X decoder, LVC...level conversion circuit, FF...launch circuit,
Vig-G, Vw-G...control voltage generation circuit, IO
B: Input/output circuit, WELL: Well area

Claims (1)

[Claims] 1. A CMOS circuit is formed with a well region in which a memory cell consisting of an address selection MOSFET provided on the drain side of the MNOS transistor and an isolation MOSFET provided on the source side of the MNOS transistor is formed. A well region in which a first conductivity type MOSFET is formed, and a second conductivity type MOSFET forming the well region and a CMOS circuit.
a second conductivity type MOSFET that supplies a predetermined voltage according to a control signal to a common source line shared by the isolation MOSFET; A MOSFET of a second conductivity type that short-circuits the common source line and a word line to which the gate of the MNOS transistor is coupled during operation.
An EEPROM device comprising: 2. Writing/erasing to the above MNOS transistor is as follows:
2. The EEPROM device according to claim 1, wherein the EEPROM device is operated using a voltage difference between a negative high voltage and a positive relatively low power supply voltage. 3. The scope of the claim characterized in that the change in each potential of the memory cell performing the write/erase operation is controlled by a timing signal formed based on a constant periodic pulse signal. E described in paragraph 1 or 2
EPROM device.