JPS6246356A - Cpu board - Google Patents

Abstract

PURPOSE:To protect a RAM from an adverse influence through an external bus by using some part of the RAM in common and the remaining part exclusively for a program and work. CONSTITUTION:In order for an internal access to make an access to the all areas in the RAM4, the bus of an internal address 24 is connected to an internal access request deciding circuit 27 and an address switch 30. In terms of an external access, an external access request deciding circuit 25 and the external address input part of the address switch 30 do not input all the external addresses, but fix some part in terms of hardware, that is, limit it, whereby only some part of the RAM4 is accessable.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a CPU board, and relates to a multi-master system system that mutually sends and receives data via a shared memory. This invention relates to a CPU board that uses a memory access method in which other masters are not affected even when the CPU board is in use.

[Background of the invention]

Conventionally, as described in Japanese Utility Model Application Publication No. 59-126331, the entire area of the dual port RAM is accessed by a dual port control circuit.
The PU work area and program area are separate dedicated RAs.
By having M, the contents were protected.

However, the above method increases the number of RAMs, making them expensive, and also requires dual-port RAM.
There was a problem that not all areas were necessarily used, resulting in waste.

In order to cope with this problem, according to the present invention, the number of RAMs can be reduced, the contents of programs and works are protected, and they are not adversely affected by the external bus.

(Object of the Invention) The present invention solves the drawbacks of the prior art described above, protects the contents of programs and works from being adversely affected by external buses, and efficiently uses RAM without wasting it. The purpose of this invention is to provide a CPU board that can be manufactured at low cost.

[Summary of the invention]

The configuration of the CPU board according to the present invention includes a CPU and the CPU board.
A ROM for the program of the PU, a RAM used for the program and work of the CPU and for exchanging commands, status, data, etc. between the CPU and an external bus, and access of the CPU to the RAM. A CPU board having a control circuit for controlling access from the external bus,
Of the above-mentioned RAM, an area that can be shared by the above-mentioned external bus and the above-mentioned CPU is the above-mentioned R.
The content of the program and the work is protected by limiting it to a part of the AM.

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``'a, 1. In order to achieve the above object, only one part of the RAM is used as a shared part.The other part.

By using it exclusively for programs and works.

This is to avoid any negative influence from external buses.

[Embodiments of the invention]
1. One embodiment of the CPU board according to the present invention will be described with reference to each episode.

Fig. 1 is a block diagram of a CPU board according to an embodiment of the present invention, Fig. 2 is a detailed block diagram of its control circuit, Fig. 3 is its memory map, and Fig. 4 is its external access request. A detailed block diagram of the determination circuit □ and the address switch, FIG. 5 is a block diagram of a CPU board according to a conventional example.

That is, in FIG. 1, 1 is the CPU, 6 is the ROM for the program of the CPUI, and 4 is the CPU 1.
'□ RAM is used for programs and work, and is used to exchange commands, status, data, etc. between the CPUI and the external bus 7;
This is a control circuit that controls access to the UI and access from an external bus 7, where 3 is an internal bus and 2 is an internal bus.
is an input/output control section, and these are the input/output control sections of the RAM4.

By limiting the area that can be shared by access from the external bus 7 and access from the CPUI to a portion of the RAM 4, the contents of the program and work described above are protected.

A more specific explanation is as follows.

The CPUI is configured to control external devices through the input/output control unit 2 according to programs in the ROM 6. Further, the control circuit 5 controls access to the RAM 4 from the CPUI and the external bus 7. The internal bus 3 connects CPtJl, input/output control unit 2, ROM 6 . The control circuit 5 is connected thereto.

A plurality of boards similar to the board shown in this block diagram are connected to the external bus, and a part of the shared portion of the RAM 4 can be accessed through the external bus 7 and the control circuit 5. 1□ CPtJl is connected to RAI44 through control circuit 5.
All parts of the computer can be accessed, and parts other than the shared parts are used for programs and work.

Next, regarding the above control circuit 5,
□This will be explained in more detail with reference to Figure 2.

The external access request determination circuit 25 uses the external address 22 and the external control signal 21 to determine whether or not there is an access request from the outside, and outputs an external access request signal 26 to the priority determination circuit 31. be.

The internal access request determination circuit 27 uses the internal address 24 and the internal control signal 23.

Determine whether there is an access request from inside,
It outputs an internal access request signal 28 to the priority determination circuit 31.

The priority determination circuit 31 selects one of the two access requests.
The first request is accepted and the memory address switching signal 29 is output to the address switching device 30.

At the same time, if an external access request is accepted,
By outputting the external driver access signal 37 to the external data bus driver 41, the external data bus 4
2 and the memory data bus 40, and outputs an internal WAIT signal 34 to the internal CPUI to make the internal access request wait.

Further, when the internal access request is accepted, by outputting the internal driver access signal 35 to the internal data bus driver 43.

Connects the internal data bus 44 and memory data bus 40, and connects the external WAIT signal 32 to the external CP
Output to U and make external access requests wait.

Further, a RAM access request signal 33 is output to the timing generation circuit 38.

The address switcher 30 uses a memory address switching signal 29
The accepted address is output to the RAM 4 as the memory address 36.

The timing generation circuit 38 outputs a RAM control I control signal 39 to the RAM 4 based on the RAM access request signal 33 received from the priority determination circuit 31.

As described above, reading/writing of the RAM 4 is performed.

In the above embodiment of the present invention, access from inside can access all areas of RAM4.
Internal access request determination circuit 27° and address switch 3
0 is connected to the bus with internal address 24.

For external access, external access request determination circuit 25. In the external address input section of the address switch 30, only a part of the RAM 4 can be accessed by limiting all external addresses.

Next, a memory access image will be explained using FIG. 3. FIG. 3 shows the R
It shows a memory map related to AM4.

In FIG. 3, both the external memory space and the internal memory space are 1M byte memory spaces of 0-FFFFF.

In the internal memory space, 120 bytes of memory are implemented from 0 to lFFFF, of which 0 to IDFFF
The 120 bytes are internal dedicated memory 53, and the IE
The 8th byte from OOO to lFFFF is a shared memory 54 with the outside.

Further, the space from 20000 to FFFFF is the internal memory unimplemented space 56.

As for the external memory space, an external dedicated memory 51 is mounted in the space from 0 to F7FFF, and no memory is mounted in the space from F8000 to FFFFF.

However, the external (7) CPU, etc.
The external memory unimplemented space 55 of F cannot be accessed, but when the external virtual memory 52 of F 8000-F9FFF is accessed, the shared memory 54 can be accessed via the control circuit 5 in the embodiment of the present invention. It is a thing.

In other words, for external CPU etc., F8000~F
Of the space of FFFF, only the space of F8000-F9FFF is accessed as if there is actual memory, ・1. ,,Ai au yayu,,. There are many functions that can be used.

, 1 Demonstration 8 parts 1° 0 pa 1 Details ■Clear 6・Already stated''
′! 11, FIG. 4 is a detailed block diagram of the external access request determination circuit and the at '1, . . . , pulse switching device. :1・In FIG. 4, the external access request signal 26 is ``;:
1 External memory read signal 61 and external memory write signal
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DO: is the road.
□]” As a result, in Figure 3, F8000~
・ ]F9 Transfer the external virtual memory 52 of FFF to external C
External access request signal 2 when PU etc. accesses
6 becomes "1'" and is output to the priority determination circuit 31 in FIG.

The address switch 30 has inputs of AO to A16 and inputs of BO to 8.
According to the address switching signal 29, one of the 16 inputs is outputted to CO to C15, and the external address and internal address connected to each are output from the memory address bus 36 to the memory address MA15 according to the address switching signal 29. ~Output to memory as MAO.

As can be seen from FIG. 4, all 20-2ie are input to the address switch 30 for the bus with internal address 24, but 20-2ie is input to the bus with external address 22.
Only 12 is input, and the input portions corresponding to 213 to 218 are fixed at +5V, that is, logic "11". As a result, for internal access, O~lFFF
The entire internal memory capacity of F bytes can be accessed, and for external access, 8 of IEOOO to lFFFF can be accessed.
The memory capacity is limited to bytes of memory.

However, one feature of the present invention is the above-mentioned feature.
Theory □. Let's meet, Yu, RAM4 (7) common part □
part,. 1” Yoo, A5, U3□1oA9.3ゎ. , 8゜゜゜:1''. Otta*m
at, □, □□5, r U 1” 4 knee m Ql!
'1.

When another board that shares the RAM 4 on this board through the external bus 7 becomes abnormal, the shared portion may be accessed at random, and its contents may be destroyed.

″1°′″@ @ , RAM 4 (7)'I-”
If access is enabled from C &%m"", 1], 1 CPU, 20. 8. □□,
Ah, 1. A □′ was also destroyed, and the CP
This has the negative effect of causing the UI to malfunction. 'll ・1 '1 According to the present invention, some of the shared parts are
;,], so only the shared parts are destroyed ・,,1, and the program and work are protected, so □], A, s (7
) J% * t: Yo1rCPU17! II, 81M 9
There is no % f Lt 6 : 5・]:'1,
1. Furthermore, by detecting the destruction of the shared portion, it is also possible to detect that another board connected to the external bus that caused this destruction is abnormal.

Furthermore, as in the conventional example, there are two types of RAM: RAM dedicated to the internal CPU and dual port RAM shared internally and externally.
Rather than using a method in which a single RAM is used as a RAM, one RAM can be used in two ways depending on how it is accessed, making it possible to provide products that can be used efficiently and at low cost.

That is, as mentioned above, FIG. 5 shows a conventional example, and the same symbols as those in FIG. 1 indicate the same parts. The contents of the work area and program area of the CPU were protected by having a separate RAM 8 dedicated to the CPU.

In such a device, the number of RAM increases, making it expensive, and dual port RAM is required.
There was a problem in that the entire area of l0 was not necessarily used, resulting in waste.

On the other hand, in the case of the present invention.

As mentioned above, the number of RAMs is small and inexpensive.
The contents of programs and works are protected and prevented from being adversely affected by external buses.

〔Effect of the invention〕

According to the present invention, the contents of programs and works are protected from being adversely affected by external buses.

Moreover, it is possible to provide a CPU board that can be used efficiently without having wasted RAM, and can provide a low-cost product, and can be said to be an invention with excellent practical effects.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a CPU board according to an embodiment of the present invention, Fig. 2 is a detailed block diagram of its control circuit, and Fig. 3 is its memory pin 2°, ff141m.
1t, -to'Af! FIG. 5 is a detailed block diagram of the 5yl-trxM□O, 11° and address switch. FIG. 2 is a block diagram of a CPU board according to a conventional example. 1...CPU, 2...I/O control unit, 3゛°°internal bus. 4...RAM, 5...control circuit, 6...
ROM, 7... External bus, 21... External control signal, 22... External address, 23... Internal control signal, 24... Internal address, 25... External access request determination circuit, 26 . . . External access request signal, 27 . . Internal access request determination circuit, 28 .
・Internal access request signal, 29...Memory address switching signal, 30...Address switch, 31...Priority determination circuit, 32...External WAIT signal, 33...R
AM access request signal, 34...internal WAIT signal,
35... Internal driver access signal, 36... Memory address bus, 37... External driver access signal, 38... Timing generation circuit, 39... RA
M control signal, 40... memory data bus,
41... External data bus driver, 42... External data bus, 43... Internal data bus driver, 4
4... Internal data bus, 51... External dedicated memory,
52... External virtual memory, 53... Internal dedicated memory, 54... Shared memory, 55... External memory unimplemented space, 56... Internal unimplemented space, 61 "°" External Mainly read signal/I. 62...External memory write signal, 63...OR circuit, (1 other person) 51' :: Hayao, 1 1・ ;:' 1: j: :1 1I' 1: ::'

Claims (1)

[Claims] 1. A CPU, a ROM for a program of the CPU,
A RAM used for programs and work of the CPU and for exchanging commands, status, data, etc. between the CPU and an external bus, and an access to the RAM by the CPU and an access from the external bus. C having a control circuit for controlling
In the PU board, an area of the RAM that can be shared by access from the external bus and the CPU is limited to a part of the RAM to protect the contents of the program and the work. A CPU board that is characterized by: 2. In the device described in claim 1, the control circuit determines whether there is an access request from the outside based on an external address and an external control signal, and outputs an external access request signal. a determination circuit; an internal access request determination circuit that determines whether or not there is an internal access request based on the internal address and internal control signal and outputs an internal access request signal; Accepts the request and sends the memory address switching signal to the memory address concerned.
The address switching signal causes the accepted address to be output to the RAM as a memory address.At the same time, if an external access request is accepted, the external data bus driver is sent to the external data bus driver. Outputs the access signal and internal W
The AIT signal is output to the internal CPU, and when an internal access request is accepted, the internal driver access signal is output to the internal data bus driver, and the external WAIT signal is output to the external CPU.
Furthermore, in addition to each of these outputs, a priority determination circuit is configured to output a RAM access request signal to a timing generation circuit that outputs a RAM control signal to the RAM in response to the RAM access request signal. CPU board. 3. In the device described in claim 2, the external data bus and the memory data bus are connected by outputting an external driver access signal to the external data bus driver, and the internal WAIT signal C of
The internal data bus is connected to the memory data bus by configuring the output to the PU to make the internal access request wait, and by outputting the internal driver access signal to the internal data bus driver. External WA
A CPU board is configured to output IT signals to an external CPU and wait for external access requests.