JPS6246339A - Microprogram controller - Google Patents

Abstract

PURPOSE:To expand a program storage area without adding an order control circuit used for expanding an address by temporarily stopping the microprogram action of a microprogram controller when a memory bank is selected and switched. CONSTITUTION:A bank selecting part 17 selects the memory bank, and at this time a clock stop signal output part 16 temporarily stops a clock signal CLK. As a result the microprogram executing action is stopped until the microprogram from a new memory bank is read out, thereby smoothly switching the memory bank. Accordingly, the switching of the memory bank, which is conventionally difficult, can expand the program storage area, and consequently it is unnecessary to add the order control circuit block.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In a microprogram control device having a sequential control circuit that generates fixed-length program addresses, the operation of the own microprogram is temporarily stopped.

By switching the banks of the microprogram storage memory, it is possible to expand the microprogram storage area without adding a sequential control circuit block.

[Industrial application field]

The present invention relates to a microprogram control device, and more particularly to a microprogram control device capable of expanding a microprogram storage area.

[Conventional technology]

In a general-purpose processor device system, the program storage memory and the processor device operate independently, so it is possible to expand the memory by so-called memory bank switching. That is, the processor device fetches an instruction for bank switching and executes the instruction in the following order:
You can easily switch banks.

However, in a microprogram control device, the stored program itself performs order control.

Bank switching is difficult. That is, in the microprogram control device, the program storage memory is always accessed in every cycle.5 For example, if a bank switching instruction is attempted to be performed by a microprogram reading out from the program storage memory and instructing bank switching, at that point,
Since preparations for reading from the previous bank have already been made, a malfunction may occur.

Therefore, conventionally, microprogram control devices
6) Expand the microprogram storage area in 2I=
For example, as shown in FIG. 4, the addresses of the sequential control circuits were enlarged.

In FIG. 4, 10 represents a sequence control circuit, 11-1 to 11-4 represent sequence control circuit blocks, and 12 represents a program storage memory constituted by a ROM.

Sequential control circuit output 11-1・°°°・Example
For example, 4-bit slice sequence control LS
I is '1゛□6, 3a. LSI”i
? , 1°3.7. . A. Generate 21 steps A0 to A11. Furthermore, when expanding the address, as shown in FIG.
-4 serially connected, 161: , y 1107 t
'u, 2. A. ~A IS (!: t 4゜, -h
If you use a large program storage memory 2, 1゜2 is -e! a,h'2"6・
[[Problem that the invention seeks to solve] M
In the above configuration, the sequential control circuit block
If j is serially connected and increased, there will be an additional delay time due to carry from the previous sequential control circuit block, resulting in a problem that the operating speed of the entire device will be slowed down.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In FIG. 1, 10 is a sequence control circuit, 12 is a program storage memory, 13-1 to 13-1 are memory banks, 14 is a clock supply section that supplies a clock signal CLK to this device, and 15 is a program storage memory 12. A latch register 16 is used to set the microprogram read from the latch register 15, and a clock stopper 16 outputs a signal that temporarily stops the clock signal CLK output by the clock supply unit 14 in response to a memory bank switching instruction latched in the latch register 15. A signal output section 17 represents a bank selection section that outputs a signal for selecting a memory bank in response to a memory bank switching instruction.

The order control circuit 10 inputs the fixed length addresses +A6 to A7,
Clock 1 outputted by the clock supply unit 14
(3″0°゛°゛6°116°PaJ′<7/)”
° To゛"3-2"-77) @"&:ni!, A°
~9·+717,,q addresses are supplied.

Output signal from bank selection section 17 ゝ1su・′ゝ“)′<
7913-1・13-2・Island...No.1
is enabled and its enabled memory
! The microprograms corresponding to addresses A0 to A7 are read from the bank and latched into the launch register 5 in synchronization with the clock signal CLK:
"do.

From the data loaded in register 15, 1
′ = Iku Pu Dalam's intended action side? 1 Il signal is generated, and part of the latch data is used as a jump address and other sequence control signals.
The order is fed back to the order control circuit 10.

For example, if a microprogram stored in memory bank 13-1 is stored in memory bank 13-2, i? ,=
7-(?07°°Pa5” When transferring control;
, at the control transition point of memory bank 13-1 in advance.

A program for instructing bank switching is stored.

When this bank switching instruction program is read into the launch register 15, a clock stop instruction is issued to the clock stop signal output section 16 and a selection switching instruction is issued to the bank selection section 17 at the same time. Newly replaces memory bank 13-1 with memory bank 13.
A signal for selecting -2 is output. Further, a signal for temporarily stopping the clock signal CLK is output to the clock supply section 14.

(Function) According to the present invention, the bank selection section 17 selects a memory bank, and at the time of this selection change, the clock stop signal output section 16 selects a memory bank.

Clock signal CLK is temporarily stopped.

Therefore, at the time of switching, until the microprogram is read from the new memory bank.

The microprogram execution operation of this device stops.

Memory banks can be switched smoothly. Therefore, the program storage area can be expanded by memory bank switching, which has been difficult in the past, and there is no need to add a sequential control circuit block.

〔Example〕

FIG. 2 shows a circuit diagram of an embodiment of the present invention, and FIG. 3 shows a time chart of an embodiment of the invention.

In FIG. 2, the same reference numerals as in FIG. 1 correspond to those shown in FIG. Are 11-1 and 11-3 each a sequence system? A sequence control circuit block consisting of 11LSI, 20 a weight clip flop, and 21 a bank switching address register.

22 represents a decoder, 23 represents a NOT circuit, 24 represents an AND circuit, and 25 represents a delay circuit.

In this embodiment, each memory bank is a ROM (
#1) and ROM (#2). There may be three or more memory banks.

Two examples are shown to simplify the explanation.

The sequence control circuit block 11 is a 4-bit slice sequence control LSI, and since three pieces are serially connected, it outputs a total of 12 bits of address As'''A.R.
OM (#1) and ROM (#2) each have a capacity that can be addressed by 12 bits of addresses A0 to AII.

The bank switching address register 21 holds information on address bits A lz -A II, which can be said to be an extension of the address. The output of the bank switching address register 21 is decoded by the decoder 22 and stored in the ROM (#
1), becomes the chip selection signal C8 of ROM (#2).

Bank switching address register 21 and decoder 22
corresponds to the bank selection section 17 shown in FIG.

Weight clip flop 20. A NOT circuit 23, an AND circuit 24, etc. are connected to the clock stop signal output section 1 shown in FIG.
It can be considered that it corresponds to 6. The data latched in the launch register 15 causes the wait flip-flop 20
is set.

Knot circuit 23. The AND circuit 24 stops the supply of the clock signal CLK. on the other hand.

After being delayed for a predetermined time by the delay circuit 25, the clock signal CLK becomes a reset signal to the weight flip-flop 20.
0 is reset after a predetermined time and the clock signal CL
K is again supplied to the sequence control circuit 10 and the like.

The operation at the time of bank switching is as shown in FIG.

For example, after a microprogram with operation N.

Assume that there is a microprogram that instructs bank switching. This bank switching instruction microprogram has a bit field for setting the wait flip-flop 20 and a bit field for updating the bank switching address register 21. When a microprogram instructing bank switching is read from the program storage memory 12 and latched into the latch register 15 in synchronization with the primary clock signal,
Weight flip-flop 20 is cented. As a result, the supply of the clock signal is stopped, and the device enters a wait state. That is, as shown in FIG. 3, the output of one clock's worth of signals is suppressed.

On the other hand, at the same time as the wait flip-flop 20 is set, the bank switching address register 21 is updated. Therefore, the number of memory banks selected in the program storage memory 12 is 1, for example, from ROM (#1) to ROM (#2).
)become. Since the supply of the clock signal is stopped for one clock, when the supply of the primary clock signal is resumed, the microprogram from the switched ROM (#2) will be latched into the launch register 15. be done. In Figure 3, the shaded area is the ROM (
This is the part related to #2). ROM (#2) to RO
Switching to M (#1) is also possible in the same way. Further, even if there are three or more memory banks, it is possible to expand the memory banks in the same way by using the address focus provided in the bank switching address register 21.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to expand the program storage area without adding a sequential control circuit block for address expansion. Therefore, there is no delay associated with address generation.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a circuit diagram of one embodiment of the present invention, and FIG. 3 is a time chart of one embodiment of the present invention. FIG. 4 is a diagram illustrating problems of the conventional method. In the figure, 10 is a sequence control circuit, 12 is a program storage memory, and 13-1-13-i is a memory bank. 14 is a clock supply section, and 15 is a launch register. 16 represents a clock stop signal output section, and 17 represents a bank selection section. Patent applicant Fujitsu Limited
6 Representative Patent Attorney Hiroshi Mori (1 other person)
1+I R Tsukimoto #Akari-・Kisegui 4ko Mart
Figure 3 Figure 3! [(

Claims (1)

[Scope of Claims] A microprogram control device comprising a memory (12) in which a microprogram is stored and a sequence control circuit (10) that generates a fixed-length program address in synchronization with a clock signal, comprising: The memory (12) in which is stored includes a plurality of memory banks (12), each of which is supplied with a fixed length program address generated by the sequence control circuit (10).
3-1, 13-2, . . . ), and a bank selection means (17) for activating any one of the memory banks; and a memory according to a microprogram read from the memory (12). clock stop means (16) for temporarily stopping the clock signal supplied to the sequence control circuit (10) in response to a bank switching instruction; A microprogram control device characterized in that the clock stop means (16) temporarily stops the operation of the own microprogram.