JPH03260832A - Microprogram controller - Google Patents

Abstract

PURPOSE:To realize flexible and high speed control of a microprogram by adding the microprogram storage part switch information to the microinstructions of both high-speed and low-speed microprogram storage parts and at the same time performing the updating control of an address register and the selection control of a selection part in accordance with the switch information. CONSTITUTION:A high-speed microprogram storage part 1 is provided together with a low-speed microprogram storage part 2, an address register 3 which reads the microprograms out of both parts 1 and 2, a sequence control part 4, a selection part 5 which outputs selectively the microinstructions read out of both parts 1 and 2, and a read control part 6. The part 6 adds the storage part switch information C to each microinstruction to store them in both parts 1 and 2. Then the part 6 controls a selector 5 in accordance with the switch information when the microinstruction is read out and at the same time performs the updating control of the register 3 to control the read timings of both parts 1 and 2. Thus the flexible control of a microprogram is attained.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problems (Fig. 1) Working example (a) Description of one example ( Figures 2 to 4) (b)
Description of other embodiments Effects of the invention [Summary] Regarding a microprogram control device having a microprogram storage unit that combines a high speed storage element and a low speed storage element, by performing switching using a microprogram,
The purpose is to realize flexible and high-speed microprogram control, and it consists of a high-speed microprogram storage section, a low-speed microprogram storage section, an address register for successive access to both microprogram storage sections, and It has a sequence control unit that outputs a read microprogram address to the address register, and a selection unit that selects and outputs a read microinstruction from both microprogram storage units. In a microprogram control device that selects and outputs a read microinstruction, microprogram storage unit switching information is added to the microinstructions in both microprogram storage units, and update control of the address register is performed in accordance with the switching information. , a readout control section for controlling selection of the selection section is provided.

[Industrial application field]

The present invention relates to a microprogram control device having a microprogram storage unit that combines high-speed storage elements and low-speed storage elements.

Microprogram control is performed by outputting a plurality of microinstruction sequences for one macroinstruction.

With recent advances in microprogram control, storage elements that store microinstructions are required to be high-speed and large-capacity.

These two requirements are generally contradictory.

Therefore, by configuring the microprogram storage section by using low-speed, large-capacity memory elements for parts that do not require relatively high speed, and using high-speed, small-capacity memory elements for other parts, it is possible to meet the two requirements. can be fulfilled.

[Conventional technology]

Conventional high-speed microprogram storage section (hereinafter referred to as high-speed C3) and low-speed microprogram storage section (hereinafter referred to as low-speed C5)
In a microprogram storage device that combines a high-speed C3 and a low-speed C3, the switching between high-speed C3 and low-speed C3 is determined by hardware based on a certain timing.

For example, for a macro instruction, up to the first or second micro instruction is read from the high speed C3, and thereafter from the low speed C3.

[Problem to be solved by the invention]

However, the conventional technology has the following problems.

■ Since switching between high speed C5 and low speed C3 is determined by hardware, it is not possible to switch dynamically from a program, making flexible control difficult.

(2) Since the switching occurs at a fixed timing, the number of microinstructions read from the high speed C8 for one macroinstruction is limited, and it is difficult to perform high speed control by increasing the number of microinstructions read from the high speed C3.

Therefore, an object of the present invention is to provide a microprogram control device that can realize flexible and high-speed microprogram control by performing switching using a microprogram.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

As shown in FIG. 1, the present invention includes a high-speed microprogram storage section l, a low-speed microprogram storage section 2,
an address register 3 for reading out both microprogram storage units 1.2, a sequence control unit 4 that outputs a microprogram address according to a macro instruction to the address register 3, and both microprogram storage units 1.
．． a selection unit 5 that selects and outputs the read microinstruction of No. 2;
In a microprogram control device which selects and outputs a read microinstruction from both microprogram storage units 1.2 in response to an l macroinstruction, A read control section 6 is provided which adds storage section switching information and controls updating of the address register 3 and selection control of the selection section 5 in accordance with the switching information.

[Effect]

In the present invention, storage unit switching information C is added to each microinstruction and stored in each storage unit 1.2, and when reading the microinstruction, the selection unit 5 is controlled according to the switching information, and the address register 3 is performed to control the read timing of the high-speed and low-speed storage sections 1.2.

Therefore, it is possible to control switching between the high-speed storage section and the low-speed storage section on the microprogram, and flexible microprogram control is possible, and there are no restrictions on microinstructions for high-speed reading.

〔Example〕

(a) Description of an Embodiment FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of its microinstruction sequence.

In the figure, the same components as those shown in FIG. 1 are indicated by the same symbols. 5a is a micro selector, and
The 5I read microinstruction and the low speed C32 read microinstruction are selected and output by the switching output of the read control unit 6, and 5b is a switching bit selector that reads out the high speed C3I switching bit and the low speed C32 switching bit. Selective output is performed by the switching output of the control section 6, and these correspond to the selection section 5 in FIG.

7 is a microinstruction register, and microselector 5
The microinstruction from a is set by the clock CLOCK.

The read control unit 6 performs an AND operation between the switching bit of the switching pit selector 5b and the q output of the D-7 lip-flop D-FF, and outputs a micro (p) stop signal to the address register 3 and the micro instruction register.
ND, and a D-flip-flop D-FF which latches the micro stop signal of the AND gate and inputs the Q output to the AND gate.

The high-speed C3I, for example, has an access time of 1 clock, and stores frequently used "load" and "store J" instructions and arithmetic micro-instructions, while the low-speed C32 has an access time of 2 clocks, for example. , and other less frequently used microinstructions are stored.

A 1-bit switching bit is added to each microinstruction as shown in FIG. 3, and the switching bit indicates the storage section to which the next microinstruction belongs. 0″ indicates high speed C3I.

As shown in Figure 3, there are five microinstructions for one macroinstruction, and the execution order shown in the figure is microinstructions 1 and 2.
Assuming that microinstruction 3.4 is read from high-speed C3I, microinstruction 3.4 is read from low-speed C32, and microinstruction 5 is read from high-speed C3I, the switching bits attached to each microinstruction are "0", "1", and "I" as shown in the figure. o” becomes “o”.

Microinstructions 1 and 2.5 are stored in the high speed C3I, and microinstructions 3.4 are stored in the low speed C32.

FIG. 4 is an explanatory diagram of the operation of one embodiment of the present invention.

■ The machine language is read from the main memory (not shown), converted into macro instructions by the compiler, and the psigence control unit 4
given to.

The μ sequence control unit 4 first sets the micro start address a of this macro instruction in the address register 3.

At the same time, both high speed C3I and low speed C32 are read accessed by address a of address register 3.

In this case, it is assumed that the rain selectors 5a and 5b have selected the high speed C3I side.

(2) The high-speed C3I reads microinstruction 1 at address a in one clock, and sets it in the microinstruction register 7 at the beginning of CLOCK2 via the microselector 5a.

On the other hand, the switching bit "0" of the microinstruction 1 is input to the AND gate AND from the selector 5b, but the p stop signal is not issued.

Therefore, at the rising edge of clock 2, the next microaddress b included in microinstruction l of microinstruction register 7
The μ sequence control unit 4 receives this and updates the address register 3 to address b.

■ As a result, both the high-speed C3I and the low-speed C52 are read accessed, and the microinstruction 2 of the high-speed C3I is transferred to the microinstruction register 7 via the microselector 5a.
Set at the beginning of LOCK3.

At the same time, the address register 3 is updated with the next microaddress C included in the microinstruction 2.

On the other hand, since the switching bit of microinstruction 2 is “1”,
AND gate AN of the read control unit 6 via the selector 5b
A micro stop signal is output from D, and both selectors 5a and 5b are switched to the low speed C32 side.

(2) At the fourth rise of CLOCK4, since the micro stop signal is applied to the address register 3 and the micro instruction register 7, updating of these registers 3 and 7 by the clock is inhibited.

At the rising edge of CLOCK4, the D-flip-flop D-FF of the read control unit 6 latches the micro stop signal of the AND gate AND, and sets its Q output to low level.
Close the 1-AND and turn off the micro stop signal.

Therefore, address register 3 stores micro address C as 2
The clock is held to guarantee the access time of the low-speed C32.

■ At the next rising edge of the fifth CLOCK5, the low-speed C32 microinstruction 3 that took two clocks is read out, set in the microinstruction register 7 via the selector 5a, and the next microinstruction included in this microinstruction 3 is read out. d updates address register 3.

At the same time, the switching bit "l" of the microinstruction 3 of the low speed C32 is input from the selector 5b.

The D-flip-flop D-FF releases the latch when CLOCK5 rises, and the AND gate AND is opened by the Q output, so a micro stop signal is issued from the AND gate AND to the register 3.7.

Also, by switching bit "1", both selectors 5a and 5b
maintains the selection of low speed C52@.

■ Similarly to ■, at the rising edge of the 6th CLOCK6,
The micro-stop signal inhibits the updating of both registers 3.7 by the clock.

Also, at the rising edge of CLOCK6, the D-flip-flop D
-FF latches the micro stop signal of AND gate AND, sets its Q output to low level, and
Close ND to turn off the micro stop output.

Therefore, the address register 3 stores the micro address d by 2.
It holds the clock time and guarantees the access time of the low-speed CS2.

■ At the rising edge of the next 7th CLOCK7, the low speed
32 micro-instructions 4 are read out and set in the micro-instruction register 7 via the selector 5a, and the next micro-address C included in this micro-instruction 4 updates the address register 3.

At the same time, the switching bit "0" of the microinstruction 4 of the low speed CS2 is manually set by the selector 5b.

The D-flip-flop D-FF releases the latch and opens the AND gate AND at the rising edge of CLOCK7, but since the switching bit is "O", no micro stop signal is issued.

Also, by this switching bit "0", both selectors 5a, 5
b is switched to the high speed C3I side.

■ As a result, the read microinstruction 5 from the high-speed C3I is sent to the microinstruction register 7 at the rising edge of CLOCK8.
is set to

At this time, since the microinstruction 5 is the last in the microinstruction sequence, data indicating this is included, so the p-sequence control unit 4 sees this and ends the microaddress.

In this way, a switching bit is provided in the microinstruction, and according to the switching bit, the selectors 5a and 5b are switched and the register 3.7 is controlled, and when accessing the low-speed C32, one clock is inhibited and the read timing is changed. Control.

(b) Description of other embodiments In the above embodiment, the access time l clock is high-speed C
5 and low speed C3 with an access time of 2 clocks has been described, but other access times may be used.

Although the present invention has been described above with reference to examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, the following effects are achieved.

■ Switching between the high-speed memory section and the low-speed memory section can be achieved using a microprogram, allowing for flexible microprogram control that is optimal in terms of speed and capacity.

■ Since switching is flexible, there is no limit to the number of microinstructions that can be read at high speed, allowing full performance to be achieved.

[Brief explanation of drawings]

Figure 1 is a diagram of the principle of the present invention, Figure 2 is a diagram of the configuration of an embodiment of the invention, Figure 3 is an illustration of the microinstruction sequence in Figure 2, and Figure 4 is an illustration of the operation of an embodiment of the invention. It is. In the figure, 1--high-speed microprogram storage section, 2--low-speed micro-program storage section, 3--address register, 4--sequence control section, 5--selection section, 6--readout@cabin section.

Claims (1)

[Claims] A high-speed microprogram storage section (1), a low-speed microprogram storage section (2), an address register (3) for reading both microprogram storage sections (1, 2), and a macro. A sequence control unit (4) outputs a microprogram address according to the instruction to the address register (3).
), and a selection unit (5) that selects and outputs the read microinstruction of both the microprogram storage units (1, 2), and for one macroinstruction, the selection unit (5) selects and outputs the reading microinstruction of both the microprogram storage units (1, 2).
, 2), in a microprogram control device that selects and outputs a read microinstruction, adds microprogram storage unit switching information to the microinstructions in both microprogram storage units (1, 2), and adds microprogram storage unit switching information to the microinstructions in both microprogram storage units (1, 2), and A microprogram control device characterized in that a read control section (6) is provided for controlling updating of the address register (3) and controlling selection of the selection section (5).