JPS6246066B2 - - Google Patents

Info

Publication number
JPS6246066B2
JPS6246066B2 JP56164726A JP16472681A JPS6246066B2 JP S6246066 B2 JPS6246066 B2 JP S6246066B2 JP 56164726 A JP56164726 A JP 56164726A JP 16472681 A JP16472681 A JP 16472681A JP S6246066 B2 JPS6246066 B2 JP S6246066B2
Authority
JP
Japan
Prior art keywords
alloy
plating
wire
thickness
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56164726A
Other languages
Japanese (ja)
Other versions
JPS5882406A (en
Inventor
Shoji Shiga
Satoshi Suzuki
Noryoshi Kiso
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Electric Co Ltd
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Priority to JP56164726A priority Critical patent/JPS5882406A/en
Publication of JPS5882406A publication Critical patent/JPS5882406A/en
Publication of JPS6246066B2 publication Critical patent/JPS6246066B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/4557Plural coating layers
    • H01L2224/45572Two-layer stack coating

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Insulated Conductors (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は耐食性と半田付け性を改善した銀又は
銀合金被覆ダイオードリード線とその製造方法に
関するものである。 銀又は銀合金被覆線の芯線の特性に加えて銀特
有の優れた耐食性と半田付け性を有するため、
種々の用途に用いられている。 例えば、CuやCu−Ag、Cu−Sn、Cu−Znなど
の合金線にAgを被覆した線は、芯線の機械的特
性と導電性に加えて銀特有の優れた耐食性と半田
付け性を有するところから電子部品のリード線や
電子機器内の導体として広く利用されており、
Ag被覆の厚さは耐食性、半田付け性や経済的な
面から一般には1〜10μ程度である。このような
Ag被覆線を高温環境に晒すと芯線Cuの拡散によ
つて外観変色を起し、半田付け性を著しく劣化す
る。これを避けるため、芯線とAg被覆との間に
Ni又はNi合金層を設けたものが実用化されてい
る。Ni又はNi合金層は拡散バリヤーとなつて芯
線CuのAg被覆層への拡散進出を抑えるもので、
Ag被覆厚さが薄くても表面品質の低下が起ら
ず、経済的であるとされている。 しかしながら、このようなAg被覆線を半田付
けし、ある程度の半田肉盛りを必要とするダイオ
ードリード線の場合でも半田の濡れ浸透が活発
で、迅速に薄く濡れ拡がるため半田肉盛り作業が
困難であつた。また高温環境に晒すと、大気中の
酸素がAg層内部に活発に浸透し、その結果Ni又
はNi合金層の表面が酸化してAg層が剥離し易く
なり、ダイオードリード線の信頼性を低下するば
かりか、半田強度をも低下する。従つて、ダイオ
ードリード線ではNi又はNi合金層の使用を止
め、厚いAg被覆を行なつたものを使用してい
る。 本発明はこれに鑑み、種々研究の結果、耐食性
と半田付け性が優れ、かつ半田肉盛りが容易で、
高価なAgを節約し得る銀又は銀合金被覆ダイオ
ードリード線とその製造方法を開発したものであ
る。 本発明ダイオードリード線は、芯線の最外周に
Ag又はAg合金層を設けた線において、無酸素Cu
またはCu合金からなる芯線上にNi、Co又はこれ
らの合金層と、Zn、Sn、In、Cd又はこれらの合
金層とを順次形成し、その上にAg又はAg合金層
を設けたことを特徴とするものである。 またダイオードリード線の製造方法は、無酸素
Cu又はCu合金からなる芯線上にNi、Coまたはこ
れらの合金をメツキした後、Zn、Sn、In、Cd又
はこれらの合金をメツキし、その上にAg又はAg
合金をメツキすることを特徴とするものである。 即ち、本発明ダイオードリード線は第1図に示
すように、無酸素Cu又はCu合金からなる芯線1
の周面にNi、Co又はこれらの合金層2を形成
し、その上にZn、Sn、In、Cd又はこれらの合金
層3を形成し、その上にAg又はAg合金層4を設
けたものである。Ni、Co又はこれらの合金層
(以下第1中間層と記載する)としてはNi、Coの
外、例えば、Ni−Co、Ni−P、Ni−B、Ni−
Sn、Ni−Zn、Co−P、Co−Sn合金等であり、そ
の厚さは0.1〜5μ程度で十分である。 Zn、Sn、In、Cd又はこれらの合金層(以下第
2中間層と記載する)としては、Zn、In、Cdの
外、例えばZn−Cu、Zn−Cd、Sn−In、Sn−
Pb、Sn−Cu、Sn−Zn等であり、これら金属又は
合金の内いずれか1種又は2種以上を積層して第
2中間層を形成してもよく、その厚さはAg又は
Ag合金被覆厚さの1/500〜1/10とすることが望ま
しい。またAg又はAg合金層としては、Agの外に
Ag−Cu、Ag−Sb合金等があり、その厚さは通
常0.5μ以上とすることが望ましい。 本発明被覆線は以上の構成を有し、薄いAg又
はAg合金の被覆でも変色などの外観異常や剥離
を起すことなく、半田付け性も低下することな
く、適度の半田濡れ拡がり性を示し、適度の半田
肉盛りが容易である。これ等の効果は、リード線
へのヘツダー加工された先端部にSiチツプを高温
で半田付けする場合に半田濡れ拡がり性が適度
で、チツプを保持する半田肉盛りが容易となり、
その後チツプ部を樹脂封止するため、高温で長時
間処理してもリード線の半田付け性は低下しな
い。 このような効果が得られる理由は必ずしも明確
ではないが、第2中間層の一部がAg又はAg合金
中に拡散して合金化し、大気中の酸素による第1
中間層の表面酸化を防止すると共に、半田の濡れ
拡がりを適度に抑えるものと考えられる。しかし
て、第2中間層の厚さがAg又はAg合金被覆厚さ
の1/500未満では第1中間層の表面酸化防止が不
十分となり、1/10を越えると半田付け性が低下す
るようになる。 このような、本発明ダイオードリード線は次の
ようにして作られる。即ち、無酸素Cu又はCu合
金からなる芯線表面を通常の手段により脱脂、活
性化した後、電気メツキ又は化学メツキにより第
1中間層、第2中間層、Ag又はAg合金被覆層を
連続して順次形成することにより容易に製造する
ことができる。 以下、本発明を実施例について詳細に説明す
る。 実施例 1 直径0.6mmのCu線を連続的に供給し、これを巻
取るラインに下記処理槽を連続して設け、無酸素
Cu線に厚さ1.0μのNiメツキと厚さ0.05μのZnメ
ツキと厚さ1.5μのAgメツキを連続的に行なつ
て、本発明ダイオードリード線を製造した。 (1) カソード脱脂 NaOH20g/、10A/dm2、10sec (2) 水洗 清水、5sec (3) 酸洗 H2SO4100g/、5sec (4) 水洗 清水、5sec (5) Niメツキ NiSO4240g/、NiCl250g/、H3BO330
g/、浴温40℃、5A/dm2、60sec (6) 水洗 清水、5sec (7) Znメツキ ZnCN60g/、NaCN40g/、NaOH80
g/、浴温R.T、1A/dm2、20sec (8) 水洗 清水、5sec (9) Agスイライクメツキ AgCN3g/、KCN40g/、浴温R.T、
10A/dm2、3sec (10) Agメツキ AgCN50g/、KCN100g/、浴温R.
T、3A/dm2、55sec (11) 水洗 清水、10sec (12) 乾燥 実施例 2 実施例1において、(5)のNiメツキと(7)のZnメ
ツキに代えて下記処理槽を設け、無酸素Cu線に
厚さ0.25μの約10%Co−Ni合金メツキと、厚さ
0.1μの約30%Zn−Cu合金メツキと厚さ1.5μの
Agメツキを連続的に行なつて本発明ダイオード
リード線を製造した。 (5) Ni−Co合金メツキ NiSo4240g/、CoSo415g/、NiCl220
g/、H3BO430g/、浴温40℃、0.4A/
dm2、30sec (7) Cu−Zn合金メツキ CuCN30g/、Zn(CN)210g/、
NaCN50g/、NA2CO330g/、浴温40
℃、0.4A/cm2、30sec 実施例 3 実施例2において、(7)のCu−Zn合金メツキに
代えて下記処理槽を設け、無酸素Cu線に厚さ
0.25μの約10%Co−Ni合金メツキと、厚さ0.1μ
のSnメツキと厚さ1.5μのAgメツキを連続的に行
なつて本発明ダイオードリード線を製造した。 (7) Snメツキ SnSO4100g/、H2SO450g/、β−ナ
フトール1g/、ニカワ2g/、浴温R.
T、1A/dm2、15sec 実施例 4 実施例1において(5)のNiメツキと(7)のZnメツ
キに代えて下記処理槽を設け、無酸素Cu線に厚
さ1.5μの約5%P−Ni合金メツキと厚さ0.5μの
Inメツキと厚さ1.5μのAgメツキを連続的に行な
つて本発明ダイオードリード線を製造した。 (5) Ni−P合金メツキ NiSO4180g/、NiCl230g/、H3BO330
g/、H3PO310g/、浴温45℃、5A/d
m2、90sec (7) Inメツキ In(BF43250g/、H3BO415g/、
NH4BF450g/、浴温R.T、5A/dm2
20sec 実施例 5 実施例4において、(7)のInメツキに代えて下記
処理槽を設け、無酸素Cu線に厚さ1.5μの約5%
P−Ni合金メツキと厚さ0.1μのCdメツキと厚さ
1.5μのAgメツキを連続的に行なつて本発明ダイ
オードリード線を製造した。 (7) Cdメツキ CdCN35g/、NaCN70g/、Na2CO340
g/、浴温30℃、2.5A/dm2、6sec 実施例 6 実施例4において(7)のInメツキに代えて下記の
処理槽を設け、無酸素Cu線に厚さ1.5μの約5%
P−Ni合金メツキと厚さ0.1μの約10%Sn−Cu合
金メツキと厚さ1.5μのAgメツキを連続的に行な
い本発明ダイオードリード線を製造した。 (7) Cu−Sn合金メツキ CuCN30g/、K2SnO335g/、KCN70
g/、KOH12g/、ロツシエル塩30g/
、浴温60℃、5A/dm2、5sec 実施例 7 実施例2において(5)のNi−Co合金メツキに代
えて下記処理槽を設け、無酸素Cu線に厚さ0.3μ
のCoメツキと、厚さ0.1μの約30%Zn−Cu合金メ
ツキと厚さ1.5μのAgメツキを連続的に行なつて
本発明ダイオードリード線を製造した。 (5) Coメツキ CoSO4400g/、NaCl20g/、H3BO345
g/、浴温R.T、5A/dm2、18sec 実施例 8 実施例7において(10)のAgメツキに代えて下記
処理槽を設け、無酸素Cu線に厚さ0.3μのCoメツ
キと、厚さ0.1μの約3%Zn−Cu合金メツキと厚
さ1.5μの約2%Sb−Ag合金メツキを連続的に行
なつて本発明ダイオードリード線を製造した。 (10) Ag−Sb合金メツキ AgCN12g/、KCN40g/、酒石酸アン
チモルカリウム25g/、酒石酸カリウムナト
リウム25g/、KOH15g/、浴温R.T、
4A/dm2、40sec 比較例 1 実施例1において(5)のNiメツキと(7)のZnメツ
キを省略し、無酸素Cu線上に厚さ1.5μのAgメツ
キを行ない、Ag被覆Cu線を製造した。 比較例 2 比較例1において(10)のAgメツキ時間を2倍に
し、無酸素Cu線上に厚さ3.0μのAgメツキを行な
い、Ag被覆Cu線を製造した。 比較例 3 比較例1において(7)のZnメツキを省略し、無
酸素Cu線に厚さ1.0μのNiメツキと厚さ1.5μの
Agメツキを連続的に行なつてAg被覆Cu線を製造
した。 比較例 4 比較例3において(10)のAgメツキ時間を2倍に
し、無酸素Cu線上に厚さ1.0μのNiメツキと、厚
さ3.0μのAgメツキを連続的に行なつてAg被覆
Cu線を製造した。 このようにして製造した各種ダイオードリード
線について、ダイオード組立工程を模して、H2
気流中310℃の温度で15分間加熱処理した後、大
気中250℃の温度で10時間加熱処理し、各熱処理
後のダイオードリード線を240℃の温度に加熱し
た共晶半田浴中に2秒間デツプし、表面の半田付
着面積を目視により比較した。また両熱処理後の
ダイオードリード線をゲージ長さ160mmで80回捻
回し、Ag被覆の剥離状態を比較した。これらの
結果を第1表に示す。
The present invention relates to a silver or silver alloy coated diode lead wire with improved corrosion resistance and solderability, and a method for manufacturing the same. In addition to the characteristics of the core wire of silver or silver alloy coated wire, it has the excellent corrosion resistance and solderability peculiar to silver.
It is used for various purposes. For example, alloy wires such as Cu, Cu-Ag, Cu-Sn, and Cu-Zn coated with Ag have excellent corrosion resistance and solderability unique to silver, in addition to the mechanical properties and conductivity of the core wire. For this reason, it is widely used as lead wires for electronic components and conductors in electronic devices.
The thickness of the Ag coating is generally about 1 to 10 μm from the viewpoints of corrosion resistance, solderability, and economy. like this
When Ag-coated wire is exposed to a high-temperature environment, the appearance discolors due to the diffusion of Cu in the core wire, which significantly deteriorates solderability. To avoid this, between the core wire and the Ag coating,
Those provided with a Ni or Ni alloy layer have been put into practical use. The Ni or Ni alloy layer acts as a diffusion barrier and prevents the core wire Cu from diffusing into the Ag coating layer.
Even if the Ag coating thickness is thin, surface quality does not deteriorate and it is said to be economical. However, even in the case of diode lead wires that require a certain amount of solder build-up by soldering Ag-coated wires, the solder wets and penetrates actively and quickly spreads in a thin layer, making it difficult to build up the solder. Ta. Furthermore, when exposed to a high temperature environment, oxygen in the atmosphere actively penetrates into the Ag layer, resulting in oxidation of the surface of the Ni or Ni alloy layer, making the Ag layer more likely to peel off, reducing the reliability of the diode lead wire. Not only this, but also the solder strength is reduced. Therefore, the use of a Ni or Ni alloy layer is no longer used in diode lead wires, and those with a thick Ag coating are used instead. In view of this, and as a result of various studies, the present invention has excellent corrosion resistance and solderability, and is easy to apply solder overlay.
We have developed a silver or silver alloy coated diode lead wire and its manufacturing method that can save expensive Ag. The diode lead wire of the present invention has a
In wires with Ag or Ag alloy layer, oxygen-free Cu
Or, a layer of Ni, Co, or an alloy thereof, and a layer of Zn, Sn, In, Cd, or an alloy thereof are sequentially formed on a core wire made of a Cu alloy, and a layer of Ag or an Ag alloy is provided thereon. That is. Additionally, the manufacturing method for diode lead wires is oxygen-free.
After plating Ni, Co or these alloys on a core wire made of Cu or Cu alloy, Zn, Sn, In, Cd or these alloys are plated, and then Ag or Ag
It is characterized by plating the alloy. That is, as shown in FIG. 1, the diode lead wire of the present invention has a core wire 1 made of oxygen-free Cu or Cu alloy.
Ni, Co, or an alloy layer 2 of these is formed on the circumferential surface, a layer 3 of Zn, Sn, In, Cd, or an alloy thereof is formed thereon, and a layer 4 of Ag or an Ag alloy is provided thereon. It is. In addition to Ni and Co, Ni-Co, Ni-P, Ni-B, Ni-
It is made of Sn, Ni-Zn, Co-P, Co-Sn alloy, etc., and a thickness of about 0.1 to 5 μm is sufficient. Zn, Sn, In, Cd or an alloy layer thereof (hereinafter referred to as a second intermediate layer) may include Zn, In, or Cd, such as Zn-Cu, Zn-Cd, Sn-In, Sn-
Pb, Sn-Cu, Sn-Zn, etc., and the second intermediate layer may be formed by laminating any one or two or more of these metals or alloys, and its thickness may be Ag or
It is desirable to set it to 1/500 to 1/10 of the Ag alloy coating thickness. In addition, as an Ag or Ag alloy layer, in addition to Ag,
There are Ag-Cu, Ag-Sb alloys, etc., and the thickness is usually desirably 0.5μ or more. The coated wire of the present invention has the above-mentioned structure, and exhibits appropriate solder wetting and spreading properties without causing abnormal appearance such as discoloration or peeling even with a thin Ag or Ag alloy coating, and without deteriorating solderability. It is easy to apply a suitable amount of solder. These effects are that when soldering a Si chip to the header-processed tip of a lead wire at high temperature, the solder wetting and spreading properties are appropriate, and it is easy to build up solder to hold the chip.
Since the chip portion is then sealed with resin, the solderability of the lead wires will not deteriorate even if processed at high temperatures for a long time. The reason why such an effect is obtained is not necessarily clear, but a part of the second intermediate layer diffuses into Ag or an Ag alloy and becomes alloyed, and the first intermediate layer is absorbed by oxygen in the atmosphere.
It is thought that this prevents surface oxidation of the intermediate layer and also appropriately suppresses solder wetting and spreading. However, if the thickness of the second intermediate layer is less than 1/500 of the Ag or Ag alloy coating thickness, the surface oxidation prevention of the first intermediate layer will be insufficient, and if it exceeds 1/10, the solderability will decrease. become. Such a diode lead wire of the present invention is manufactured as follows. That is, after degreasing and activating the surface of the core wire made of oxygen-free Cu or Cu alloy by normal means, the first intermediate layer, the second intermediate layer, and the Ag or Ag alloy coating layer are successively applied by electroplating or chemical plating. It can be easily manufactured by sequentially forming them. Hereinafter, the present invention will be described in detail with reference to examples. Example 1 Cu wire with a diameter of 0.6 mm is continuously supplied, and the following treatment tank is installed continuously on the line that winds it, and an oxygen-free
A diode lead wire of the present invention was manufactured by successively applying Ni plating to a thickness of 1.0μ, Zn plating to a thickness of 0.05μ, and Ag plating to a thickness of 1.5μ to a Cu wire. (1) Cathode degreasing NaOH 20g/, 10A/dm 2 , 10sec (2) Water washing Clear water, 5sec (3) Pickling H 2 SO 4 100g/, 5sec (4) Water washing Clear water, 5sec (5) Ni plating NiSO 4 240g/ , NiCl 2 50g/, H 3 BO 3 30
g/, bath temperature 40℃, 5A/dm 2 , 60sec (6) Water washing Clear water, 5sec (7) Zn plating ZnCN60g/, NaCN40g/, NaOH80
g/, bath temperature RT, 1A/dm 2 , 20sec (8) water washing clear water, 5sec (9) Ag Suirikemetsuki AgCN3g/, KCN40g/, bath temperature RT,
10A/dm 2 , 3sec (10) Ag plating AgCN50g/, KCN100g/, bath temperature R.
T, 3A/dm 2 , 55sec (11) Water washing Fresh water, 10sec (12) Drying example 2 In Example 1, the following treatment tank was installed in place of (5) Ni plating and (7) Zn plating. Approximately 10% Co-Ni alloy plating with a thickness of 0.25μ is applied to the oxygen Cu wire, and the thickness
Approximately 30% Zn-Cu alloy plating of 0.1μ and thickness of 1.5μ
A diode lead wire of the present invention was manufactured by continuously performing Ag plating. (5) Ni-Co alloy plating NiSo 4 240g/, CoSo 4 15g/, NiCl 2 20
g/, H 3 BO 4 30g/, bath temperature 40℃, 0.4A/
dm 2 , 30sec (7) Cu-Zn alloy plating CuCN30g/, Zn(CN) 2 10g/,
NaCN50g/, NA 2 CO 3 30g/, bath temperature 40
℃, 0.4A/cm 2 , 30sec Example 3 In Example 2, the following treatment bath was provided in place of the Cu-Zn alloy plating in (7), and the oxygen-free Cu wire was coated with a thickness of
Approximately 10% Co-Ni alloy plating of 0.25μ and thickness 0.1μ
A diode lead wire of the present invention was manufactured by sequentially performing Sn plating of 1.5 μm and Ag plating of 1.5 μm thick. (7) Sn plating SnSO 4 100g/, H 2 SO 4 50g/, β-naphthol 1g/, glue 2g/, bath temperature R.
T, 1A/dm 2 , 15sec Example 4 In Example 1, the following treatment bath was installed in place of the Ni plating in (5) and the Zn plating in (7), and the oxygen-free Cu wire was coated with approximately 5% of the thickness of 1.5μ. P-Ni alloy plating and thickness 0.5μ
A diode lead wire of the present invention was manufactured by successively performing In plating and Ag plating to a thickness of 1.5 μm. (5) Ni-P alloy plating NiSO 4 180g/, NiCl 2 30g/, H 3 BO 3 30
g/, H 3 PO 3 10g/, bath temperature 45℃, 5A/d
m 2 , 90sec (7) In (BF 4 ) 3 250g/, H 3 BO 4 15g/,
NH 4 BF 4 50g/, bath temperature RT, 5A/dm 2 ,
20sec Example 5 In Example 4, the following treatment tank was installed in place of the In plating in (7), and the oxygen-free Cu wire was coated with approximately 5% of the thickness of 1.5μ.
P-Ni alloy plating and 0.1μ thick Cd plating and thickness
A diode lead wire of the present invention was manufactured by continuously performing 1.5μ Ag plating. (7) Cd Mekki CdCN35g/, NaCN70g/, Na 2 CO 3 40
g/, bath temperature 30℃, 2.5A/dm 2 , 6sec Example 6 In Example 4, the following treatment tank was installed in place of the In plating in (7), and the oxygen-free Cu wire was coated with approximately 1.5μ thick %
A diode lead wire of the present invention was manufactured by sequentially performing P--Ni alloy plating, approximately 10% Sn--Cu alloy plating with a thickness of 0.1 .mu.m, and Ag plating with a thickness of 1.5 .mu.m. (7) Cu-Sn alloy plating CuCN30g/, K 2 SnO 3 35g/, KCN70
g/, KOH12g/, Lotsiel salt 30g/
, bath temperature 60℃, 5A/dm 2 , 5sec Example 7 In Example 2, the following treatment bath was provided in place of the Ni-Co alloy plating in (5), and the oxygen-free Cu wire was coated with a thickness of 0.3μ.
A diode lead wire of the present invention was manufactured by sequentially performing Co plating of 100%, approximately 30% Zn--Cu alloy plating with a thickness of 0.1μ, and Ag plating with a thickness of 1.5μ. (5) Co-metsuki CoSO 4 400g/, NaCl 20g/, H 3 BO 3 45
g/, bath temperature RT, 5 A/dm 2 , 18 sec Example 8 In Example 7, the following treatment bath was installed in place of the Ag plating in (10), and the oxygen-free Cu wire was coated with Co plating with a thickness of 0.3μ and A diode lead wire of the present invention was manufactured by successively plating a 3% Zn--Cu alloy with a thickness of 0.1 .mu.m and plating a 2% Sb--Ag alloy with a thickness of 1.5 .mu.m. (10) Ag-Sb alloy plating AgCN12g/, KCN40g/, antimol potassium tartrate 25g/, potassium sodium tartrate 25g/, KOH15g/, bath temperature RT,
4A/dm 2 , 40sec Comparative Example 1 In Example 1, Ni plating in (5) and Zn plating in (7) were omitted, and Ag plating with a thickness of 1.5μ was performed on the oxygen-free Cu wire, and the Ag-coated Cu wire was Manufactured. Comparative Example 2 In Comparative Example 1, the Ag plating time in (10) was doubled, and the oxygen-free Cu wire was plated with Ag to a thickness of 3.0 μm to produce an Ag-coated Cu wire. Comparative Example 3 In Comparative Example 1, the Zn plating in (7) was omitted, and the oxygen-free Cu wire was coated with 1.0μ thick Ni plating and 1.5μ thick Ni plating.
Ag-coated Cu wire was manufactured by continuously performing Ag plating. Comparative Example 4 In Comparative Example 3, the Ag plating time in (10) was doubled, and 1.0 μ thick Ni plating and 3.0 μ thick Ag plating were sequentially performed on the oxygen-free Cu wire to coat Ag.
Manufactured Cu wire. For the various diode lead wires manufactured in this way, H 2
After heat treatment at a temperature of 310℃ in air flow for 15 minutes, heat treatment at a temperature of 250℃ in air for 10 hours, and after each heat treatment, the diode lead wire was placed in a eutectic solder bath heated to a temperature of 240℃ for 2 seconds. The solder adhesion area on the surface was visually compared. In addition, the diode lead wire after both heat treatments was twisted 80 times with a gauge length of 160 mm, and the peeling state of the Ag coating was compared. These results are shown in Table 1.

【表】【table】

【表】 H2気流中310℃の温度で15分間処理はSiチツプ
の半田付けに相当するもので、第1表から判るよ
うに本発明実施例品はいずれも90%前後の適度の
半田付着性を示した。これに対し比較例品1、2
は半田付け性が不良であり、同3、4は半田付け
性が過剰で半田肉盛りが困難である。また大気中
250℃の温度で10時間処理は樹脂封止に相当し、
樹脂封止後の半田付け性に対応するもので、本発
明実施例品はいずれも80%以上で優れている。こ
れに対し比較例品はいずれも半田付け性が激減し
ている。また大気中250℃の温度で10時間処理後
の捻回剥離では、本発明実施例品はわずかに剥離
した程度であるのに、比較例品はいずれも剥離が
著しい。特にNi中間層を設けた比較例品3、4
においても剥離が著しいのはNi層の表面が酸化
されたためである。従来のNi中間層を設けたAg
又はAg合金被覆Cu線では半田付け性が優れてい
てもチツプ半田付けにおける半田肉盛りが困難で
あり、更に樹脂封止に耐えるためには厚さ5μ以
上の厚いAg又は合金被覆が必要であつた。 これに対し本発明によれば、はるかに薄いAg
又はAg合金被覆によりチツプ半田付けが容易で
樹脂封止に耐え、ダイオード組立を容易にし、そ
の生産性を著しく向上し得るばかりか、省銀の点
でも大きな効果を奏するものである。
[Table] Processing for 15 minutes at a temperature of 310°C in a H2 gas flow corresponds to soldering of Si chips, and as can be seen from Table 1, all of the products of the present invention had moderate solder adhesion of around 90%. showed his sexuality. In contrast, comparative example products 1 and 2
Samples 3 and 4 have poor solderability, and samples 3 and 4 have excessive solderability and are difficult to build up with solder. Also in the atmosphere
Processing at a temperature of 250℃ for 10 hours corresponds to resin sealing,
This corresponds to the solderability after resin sealing, and all of the products of the present invention are excellent with a score of 80% or more. On the other hand, the solderability of all comparative example products was drastically reduced. In addition, when peeling by twisting after treatment at a temperature of 250° C. in the atmosphere for 10 hours, the samples of the examples of the present invention peeled off only slightly, whereas the samples of the comparative examples all peeled off significantly. Especially comparative example products 3 and 4 with Ni intermediate layer.
The reason why the peeling was significant even in this case is that the surface of the Ni layer was oxidized. Ag with conventional Ni interlayer
Or, even if Ag alloy-coated Cu wire has excellent solderability, it is difficult to build up solder in chip soldering, and furthermore, a thick Ag or alloy coating with a thickness of 5μ or more is required to withstand resin encapsulation. Ta. In contrast, according to the present invention, much thinner Ag
Alternatively, the Ag alloy coating facilitates chip soldering and is resistant to resin sealing, making it easy to assemble the diode, significantly improving productivity, and also having a significant effect in terms of silver savings.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明ダイオードリード線の一例を示
す断面図である。 1……芯線、2……第1中間層、3……第2中
間層、4……Ag又はAg合金層。
FIG. 1 is a sectional view showing an example of a diode lead wire according to the present invention. 1... Core wire, 2... First intermediate layer, 3... Second intermediate layer, 4... Ag or Ag alloy layer.

Claims (1)

【特許請求の範囲】 1 芯線の最外周にAg又はAg合金層を設けた線
において、無酸素Cu又はCu合金からなる芯線上
にNi、Co又はこれらの合金層と、Zn、Sn、In、
Cd又はこれらの合金層とを順次形成し、その上
にAg又はAg合金層を設けたことを特徴とする銀
又は銀合金被覆ダイオードリード線。 2 Zn、Sn、In、Cd又はこれらの合金層の厚さ
をAg又はAg合金層の厚さの1/500乃至1/10とす
る特許請求の範囲第1項記載の銀又は銀合金被覆
ダイオードリード線。 3 無酸素Cu又はCu合金からなる芯線上にNi、
Co又はこれらの合金をメツキした後、Zn、Sn、
In、Cd又はこれらの合金をメツキし、その上に
Ag又はAg合金をメツキすることを特徴とする銀
又は銀合金被覆ダイオードリード線の製造方法。
[Claims] 1. A wire in which an Ag or Ag alloy layer is provided on the outermost periphery of the core wire, and a core wire made of oxygen-free Cu or Cu alloy is coated with Ni, Co or an alloy layer thereof, and Zn, Sn, In,
A silver or silver alloy coated diode lead wire, characterized in that a layer of Cd or an alloy thereof is sequentially formed, and a layer of Ag or an Ag alloy is provided thereon. 2. The silver or silver alloy coated diode according to claim 1, wherein the thickness of the Zn, Sn, In, Cd or alloy layer thereof is 1/500 to 1/10 of the thickness of the Ag or Ag alloy layer. Lead. 3 Ni on the core wire made of oxygen-free Cu or Cu alloy,
After plating Co or these alloys, Zn, Sn,
Plating In, Cd or their alloys, and then
A method for producing a silver or silver alloy coated diode lead wire, which comprises plating Ag or an Ag alloy.
JP56164726A 1981-10-15 1981-10-15 Silver or silver alloy coated wire and method of producing same Granted JPS5882406A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56164726A JPS5882406A (en) 1981-10-15 1981-10-15 Silver or silver alloy coated wire and method of producing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56164726A JPS5882406A (en) 1981-10-15 1981-10-15 Silver or silver alloy coated wire and method of producing same

Publications (2)

Publication Number Publication Date
JPS5882406A JPS5882406A (en) 1983-05-18
JPS6246066B2 true JPS6246066B2 (en) 1987-09-30

Family

ID=15798724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56164726A Granted JPS5882406A (en) 1981-10-15 1981-10-15 Silver or silver alloy coated wire and method of producing same

Country Status (1)

Country Link
JP (1) JPS5882406A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59228311A (en) * 1983-06-08 1984-12-21 古河電気工業株式会社 Ag-covered electric material and method of producing same
JPS63150950A (en) * 1986-12-15 1988-06-23 Shinko Electric Ind Co Ltd Package for electronic component
EP0335608B1 (en) * 1988-03-28 1995-06-14 Texas Instruments Incorporated Lead frame with reduced corrosion
JP5275504B1 (en) * 2012-06-15 2013-08-28 Jx日鉱日石金属株式会社 METAL MATERIAL FOR ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD, CONNECTOR TERMINAL USING THE SAME, CONNECTOR AND ELECTRONIC COMPONENT

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5398072A (en) * 1977-02-08 1978-08-26 Hitachi Cable Ltd Weathering wiring electrical couductor
JPS5433111A (en) * 1977-08-17 1979-03-10 Dainippon Printing Co Ltd Method of copying
JPS5472483A (en) * 1977-11-21 1979-06-09 Hitachi Cable Ltd Manufacture of heat-resistant wiring conductor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5398072A (en) * 1977-02-08 1978-08-26 Hitachi Cable Ltd Weathering wiring electrical couductor
JPS5433111A (en) * 1977-08-17 1979-03-10 Dainippon Printing Co Ltd Method of copying
JPS5472483A (en) * 1977-11-21 1979-06-09 Hitachi Cable Ltd Manufacture of heat-resistant wiring conductor

Also Published As

Publication number Publication date
JPS5882406A (en) 1983-05-18

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