JPS6246065B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a method for manufacturing an MIS type semiconductor device,
In particular, the present invention relates to a method of manufacturing an MIS type semiconductor device having a multilayer wiring structure.

When manufacturing an MIS type semiconductor device with a multilayer wiring structure, in the conventional manufacturing method, at a certain stage of the multilayer wiring formation process, the lower wiring connected to the gate of the semiconductor element is left in an electrically floating state (floating). )become. Therefore, for some reason, for example, due to the impact of ions or radicals when forming wiring connection windows by dry etching such as reactive ion etching in the interlayer insulating film, etc.
When charge is accumulated in the lower wiring and the potential of the lower wiring exceeds the withstand voltage of the gate insulating film, there is a problem that discharge occurs through the gate insulating film and the device is destroyed.

In order to eliminate the above-mentioned problems, the present invention electrically connects the lower layer wiring connected to the gate to the semiconductor substrate until the connection of the upper layer wiring is completed in the multilayer wiring formation process, so that parasitic A method for manufacturing an MIS type semiconductor device is provided, which includes means for discharging charges to a semiconductor substrate.

That is, the present invention provides a method for manufacturing an MIS type semiconductor device, in which one end of a lower wiring connected to a gate is electrically connected to a semiconductor substrate, an interlayer insulating film is formed on the lower wiring, and the interlayer insulating film is A first window exposing a connection area of the lower wiring with the upper wiring and a second window transversely exposing the area reaching the one end are formed on the interlayer insulating film, and an upper wiring material layer is formed on the interlayer insulating film. and selectively etching the upper wiring material layer to form an upper wiring on the interlayer insulating film that connects to the lower wiring at the first window. selectively etching and removing the lower layer wiring in the area exposed within;
The method is characterized by comprising a step of cutting off the lower layer wiring connected to the gate electrode from one end portion electrically connected to the semiconductor substrate.

Examples of the present invention will be described below, including a schematic top view for explaining the gist shown in FIG.
This will be explained in detail using process cross-sectional views of the embodiment and process cross-sectional views of the second example shown in FIGS. 3a to 3e.

In the method of the present invention, as shown in FIG.
Source/drain regions 2a,
When forming the contact windows 3a, 3b for the gate electrode 2b and the contact window 3c for the gate electrode 1, a contact window 3d for the semiconductor substrate (in which a diffusion region may be formed) is also formed. Then, when forming the lower layer wiring, that is, the source/drain wiring 4a, 4b and the gate wiring 4c led out from the contact window using a normal method on the lower layer insulating film, a branch wiring 4c' is provided on the gate wiring 4c, The branch wiring 4c' is connected to the semiconductor substrate (or the diffusion region formed in the region) via the contact window 3d. Then, when forming wiring connection windows (via holes) 5 for connecting upper and lower layer wiring to the interlayer insulating film provided on the substrate on which these lower layer wirings are formed,
An etching window 6 that crosses and exposes a part of the branch wiring 4c' of the gate wiring is formed on the interlayer insulating film, and then an upper wiring material layer is formed on the interlayer insulating film by a conventional method. The upper wiring material layer is selectively etched using a conventional method to form an upper wiring 7 connected to the gate wiring in the wiring connection window 5 on the interlayer insulating film, and then the etching window 6 of the interlayer insulating film is etched. The branch wiring 4c' of the gate wiring exposed inside is selectively etched away, and the lower layer gate wiring 4c, which has been connected to the upper layer wiring 7, is attached to the semiconductor substrate (or the diffusion region formed in this area). A MIS type semiconductor device is formed by cutting out the contact window 4d connected to the contact window 4d, and then following a conventional method such as forming a protective film.

Next, the method of the present invention will be explained using process cross-sectional diagrams for two embodiments.

In the first embodiment, as shown in FIG. 2a, a field oxide film 12 is formed on, for example, a P ^- type silicon (Si) substrate 11 using a conventional method, and elements are formed on the field oxide film 12. Area 13
A window exposing the protective connection forming region 14 is formed, and then a gate oxide film 1 is formed in the above region.
5 and a thin oxide film 15' are formed simultaneously, then a polycrystalline Si gate electrode 16 is formed on the gate oxide film 15, and then, as shown in FIG. 2b, using the gate electrode 16 and the field oxide film 12 as a mask, N type impurity ions (for example, phosphorus ions P ⁺ ) are selectively implanted into the surface of the substrate 11, the ion implantation regions are activated, and the N ⁺ type source/drain regions 18a and 18b are formed into protective connection formation regions in the element formation region 13. 14
An N ⁺ type diffusion region 19 is formed in FIG. 2c.
As shown in FIG. 3, a lower insulating film 17 made of phosphosilicate glass PSG or the like is formed on the substrate, and then contact windows (other than the cross section) for the source/drain regions 18a and 18b are formed in the lower insulating film 17 using a conventional method. contact windows 20 and 21 for the polycrystalline Si gate electrode 16 and the N ⁺ type diffusion region 19 are formed, and then a layer of, for example, aluminum (Al) is formed on the lower insulating film 17 by a conventional method. A gate wiring 22 having a source/drain wiring (not shown) consisting of a branch wiring 22' connected to the gate electrode 16 in the contact window 20 and connected to the N ⁺ type diffusion region 19 in the contact window 21 is formed. . Next, as shown in FIG. 2d, an interlayer insulating film 23 made of PSG or the like is formed on the substrate, and a wiring connection window 24 for the gate wiring 22 and an etching window (the branch) are formed in the interlayer insulating film 23 by a conventional method. Wiring cutting window) 2
form 5. Next, an upper wiring material layer such as an Al film is deposited on the interlayer insulating film, and then a photoresist pattern 26 is formed as shown in FIG. 2e.
The upper Al film 27' is selectively etched using the mask as a mask to form the gate wiring 22 in the wiring connection window 24.
After forming the upper layer Al wiring 27 connected to the etching window 25,
The branch wiring 22' of the gate wiring consisting of the gate wiring 22' is selectively etched away to separate the gate wiring 22 from the N ⁺ type diffusion region.

Note that in the above embodiment, the lower layer gate wiring 2
2 is the N ⁺ type diffusion region 19 and the P ^- type Si substrate 1 until the upper layer wiring 27 connected to the wiring 22 is formed.
Since it is electrically connected to the P ^- type Si substrate 11 through a reverse junction with a falling voltage of about 20 to 30 [V] formed between The high potential generated is released to the Si substrate 11 through the junction, and the gate oxide film 15 is not destroyed by the parasitic charge. In the first embodiment, the protective connection region of N ⁺ type diffusion was formed on the P ⁻ type Si substrate, but P ⁺ type diffusion may be performed using a photoresist as a mask. In that case,
The gate electrode and the P ^- type Si substrate are coupled through ohmic contact. Furthermore, even when an N ^- type Si substrate is used, the diffusion performed in the protective connection region can be of either the N ⁺ type or the P ⁺ type.

In the second embodiment, no junction is provided in the electrical connection region between the gate wiring and the substrate. That is, Figure 3a
As shown in FIG. 2, a gate oxide film 15 is formed on the element formation region 13 on the surface of the P ^- type Si substrate 11, and a thin oxide film is formed on the protective connection formation region 14 in accordance with the usual method as in the first embodiment. 15', and a field oxide film 12 is formed on other areas, and a polycrystalline Si gate electrode 16 is formed on the gate oxide film 15, and the substrate is protected as shown in FIG. 3b. A photoresist pattern 28 is formed to cover the connection forming region 14, selective implantation of N-type impurity ions (for example, phosphorus ions P ⁺ ) is performed, and then, after removing the photoresist pattern 28, the ion implantation region 14 is removed. is activated to form N ⁺ type source/drain regions 18a, 18b, and then a lower insulating film 17 is formed on the substrate in the same manner as in the previous embodiment, and then source/drain regions 18a, 18b are formed on the lower insulating film 17. contact window (not shown) for polycrystalline Si gate electrode 16 and P ^- type Si substrate 1
forming contact windows 20 and 29 for 1;
Next, on the lower insulating film 17, a gate wiring 22 having a source/drain wiring (not shown) made of Al and a branch wiring 22' connected to the gate electrode 16 and the P ^- type Si substrate 11 is formed. do.
Next, as in the first embodiment, as shown in FIG. 3d, an interlayer insulating film 23 is formed on the substrate, and a wiring connection window 24 for the gate wiring 22 and an etching window (branch wiring) are formed in the interlayer insulating film 23. cutting window) 2
Form 5. Next, an upper Al film 27' is deposited on the interlayer insulating film 23, and as shown in FIG. After forming the upper layer Al wiring 27 connected to the gate wiring 22, the branch wiring 2 of the gate wiring in the area exposed within the etching window 25 is formed.
2 is selectively etched to remove the gate wiring 2.
2 from the connection part with the P ^- type Si substrate 11. Note that in this embodiment, the branch line 2 of the gate wiring
The connection between 2' and the P ^- type Si substrate 11 is an ohmic connection, but when an N type Si substrate is used, the connection part
A shot barrier having a drop voltage of about 10 to 25 volts is formed. In either case, the charges accumulated in the gate wiring until the upper layer wiring is connected to the gate wiring are released to the substrate through the connection, so that the gate oxide film is not destroyed by the parasitic charges. There is no.

Although the first and second embodiments have been described above, the present invention is not limited to Si substrates and Al wiring. Other compound semiconductor substrates may be used, and the wiring material may be a desired metal such as titanium (Ti) or molybdenum (Mo).

It goes without saying that it can also be used in complementary MIS semiconductor devices.

As explained above, according to the present invention, when manufacturing an MIS type semiconductor device with a multilayer wiring structure, the gate insulating film is Since it is no longer destroyed, manufacturing yield is improved. In addition, in the method of the present invention, since the connection area with the substrate in the lower layer wiring connected to the gate is finally separated from the gate wiring, the wiring capacitance does not increase, and therefore the operating speed of the element does not decrease. There isn't.

[Brief explanation of the drawing]

FIG. 1 is a schematic top view for explaining the gist of the method of the present invention, FIGS. 2a to 2e are process sectional views of the first embodiment, and FIGS. 3a to 3e are process sectional views of the second embodiment. be. In the figure, 1 is a gate electrode, 2a, 2b are source/drain regions, 3a, 3b, 3c, 3d are contact windows, 4a, 4b are source/drain wires, 4c is a gate wire, and 4c' is a branch wire of the gate wire. , 5 is a wiring connection window (via hole), 6 is an etching window, 7 is an upper layer wiring, 11 is a P ^- type silicon substrate, 12 is a field oxide film, 13 is an element formation area, 14 is a protective connection formation area, 15 15' is a gate oxide film, 15' is a thin oxide film, 16 is a polycrystalline silicon gate electrode, 17 is a lower layer insulating film, 18a,
18b is an N ⁺ type source/drain region, 19 is an N ⁺
type diffusion region, 20, 21, 29 are contact windows,
22 is a gate wiring, 22' is a branch wiring, 23 is an interlayer insulating film, 24 is a wiring connection window, 25 is an etching window (branch wiring cutting window), 26 and 28 are photoresist patterns, and 27' is an upper layer aluminum. film,
27 indicates an upper layer aluminum wiring.

Claims (1)

[Claims] 1. One end of the lower layer wiring connected to the gate electrode is electrically connected to the semiconductor substrate, an interlayer insulating film is formed on the lower layer wiring, and a connection area of the lower layer wiring with the upper layer wiring is formed on the interlayer insulating film. The first step is to express
and a second window that crosses and exposes the region reaching the one end, an upper wiring material layer is formed on the interlayer insulating film, and the upper wiring material layer is selectively etched to form an interlayer After forming an upper layer interconnection connected to the lower layer interconnection in the first window on the insulating film, selectively etching away the lower layer interconnection in a region exposed within the second window of the interlayer insulating film. ,
A method for manufacturing an MIS type semiconductor device, comprising the step of cutting off a lower layer wiring connected to the gate electrode from one end electrically connected to the semiconductor substrate.