JP2655910B2 - Semiconductor device manufacturing method and semiconductor wafer used therefor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly to a dummy MOS transistor (V _th ) for measuring a threshold voltage (V _th ) formed in a scribing region of a semiconductor wafer. Below, dummy
MOS)).

[Conventional technology]

2. Description of the Related Art In recent years, with the miniaturization and high integration of elements in a semiconductor device, a conventional wet process has been replaced with a dry microfabrication process. However, with the further progress of miniaturization, the problems of the dry process are becoming more prominent. For example, although a photoresist mask (hereinafter referred to as a resist) stripping process also uses oxygen plasma, a dry process is generally performed. However, in a dry process in which a semiconductor wafer is put into such plasma and processed. In the semiconductor device, a charge-up phenomenon occurs due to charged particles such as ions and free electrons, and various problems such as deterioration of characteristics of a semiconductor device and reduction of a manufacturing yield have occurred. Gate dielectric breakdown during dry etching can be caused by the monthly Semiconductor World
World), November 1987, pp. 31-37.

By the way, on the surface of a semiconductor wafer, for example, a plasma silicon nitride (P-SiN) film is used as a first layer and a polyimide film is used as a second layer from the viewpoint of relaxing stress caused by the resin when molding a semiconductor chip with the resin. Thus, a plurality of surface protection films (hereinafter, referred to as protection films) are deposited and formed.

However, the polyimide film in the scribe region of the semiconductor wafer is removed in advance during dicing because it causes blade clogging.

On the other hand, in a semiconductor wafer in which a dummy MOS for measuring _Vth is formed in the scribing region, it is necessary to expose a bonding pad (hereinafter referred to as a pad) for extracting each electrode of the dummy MOS. The pad portion of the P-SiN film under the polyimide film is removed by etching.

Conventionally, the removal of the protective film in such a scribing area is performed by preparing a glass mask for each of the polyimide film and the P-SiN film, and performing a series of processes such as resist application, exposure, development, etching, and resist removal on each of them. Had been given. However, according to such a method, there is a problem that the manufacturing time and the number of steps are increased.

Then, as described in Japanese Patent Application No. 63-55443, the present inventor carried out the following method as a method of etching and removing the protective film in the scribing region.

That is, first, a resist film for etching the polyimide film is formed in a pattern, and the polyimide film in the scribing region is etched away using the resist pattern as a mask.

Next, using the resist pattern for removing the polyimide film and the polyimide film remaining after the etching process as a mask, the P-SiN film under the polyimide film is removed by dry etching. Therefore, the P-SiN film in the scribing region is also entirely removed.

Finally, the resist film is removed by ashing in oxygen plasma.

[Problems to be solved by the invention]

However, in the conventional technique of etching and removing the P-SiN film in the scribing region using the resist film for removing the polyimide film and the remaining polyimide film as a mask, no protective film remains on the dummy MOS. For example, at the time of dry etching of a P-SiN film or at the time of removing ashing of a resist film in plasma, the influence of the charged particles in the plasma on the dummy MOS becomes large, and the V _{th of} the dummy MOS is largely shifted. The inventor has found that this occurs.

The present invention has been made in view of the above problem, and an object of the present invention is to prevent _{Vth of} a dummy MOS formed in a scribing region from being largely changed during a manufacturing process of a semiconductor device. To provide a technique for obtaining a highly reliable semiconductor device.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of the specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, a method of manufacturing a semiconductor device having a dummy MOS transistor for measuring a threshold voltage in a scribing region at a semiconductor wafer stage, wherein the dummy MO
After forming a conductor shielding layer connected to the source electrode of the dummy MOS transistor on the upper layer of the S transistor, a plurality of surface protection films are formed on the surface of the semiconductor wafer, and the plurality of surface protection films in the scribing region are further removed. A method of manufacturing a semiconductor device including a step of performing

[Action]

According to the above-described means, during the manufacturing process of the semiconductor device, for example, when removing the protective film in the scribing region by dry etching, or when removing the resist film applied for removing the protective film in plasma,
The dummy MOS is protected from the charged particles in the plasma by the conductor shielding layer, and the generated charges and the like are removed to the source side through the conductor shielding layer, so that the V _{th of} the dummy MOS caused by the charged particles is reduced. Is prevented from significantly fluctuating.

〔Example〕

FIG. 1 is a sectional view of a main part of a semiconductor wafer used in a method of manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is an enlarged plan view of a dummy MOS in a scribing region of the semiconductor wafer, and FIG. 4 (a) to 4 (f) are cross-sectional views of a main part of the semiconductor wafer showing a method of manufacturing the semiconductor device.

A semiconductor wafer (hereinafter, referred to as a wafer) 1 used in the method for manufacturing a semiconductor device of the present embodiment shown in FIG.
A plurality of chip regions A are arranged in a lattice pattern on a main surface of the single-crystal silicon (Si) with a scribing region B therebetween.

For example, a mask ROM is configured in each chip area A.

In the scribing area B, a dummy MOS for measuring _Vth of the MOS constituting the mask ROM is provided as described later.
2 are formed. The scribing area B
Is, for example, about 160 μm.

As shown in FIG. 1, wafer 1 in chip area A
In the above, an LDD (Lightly Dopant) is formed on an n-well 4a surrounded by a field oxide film 3 made of silicon dioxide (SiO ₂ ) or the like.
The pMOS 5 having an (ed drain) structure is formed. Further, an nMOS 7 having an LDD structure is formed on the p well 6a of the wafer 1.
Although not shown, these pMOS5 and nMO
A CMOS circuit is constituted by S7, and a peripheral circuit of the mask ROM is constituted by the CMOS circuit.

pMOS5 is a source region 8 formed in an upper layer of the n-well 4a.
a and a drain region 8b, and a gate electrode 10a formed on the gate oxide film 9a. The gate electrode 10a has a polycide structure in which a silicide layer such as WSi ₂ is laminated on a polysilicon layer, for example, from the viewpoint of lowering the resistance. The polysilicon layer is, for example, about 2000 °, and the silicide layer is, for example, about 1500 °.

The nMOS 7 includes a source region 11a and a drain region 11b formed on the p-well 6a and a gate electrode 10b formed on the gate oxide film 9b. The gate electrode 10b has the same structure as the gate electrode 10a.

Although not shown, the memory cells of the mask ROM are:
For example, it is composed of a plurality of nMOSs.
Information is written according to the concentration of the impurity injected into the channel.

In the chip area A, an insulating film 12 made of SiO ₂ or the like is coated on the pMOS5, the nMOS7, and the field oxide film 3 so as to cover them.

A contact hole 13 is formed in a part of the insulating film 12 so as to reach the source region 8a, 11a and the drain region 8b, 11b of the pMOS 5 and the nMOS 7, and through the contact hole 13, aluminum (Al)-is formed. Wiring 14a made of Si-copper (Cu) or the like, source region 8a, 11a, and drain region 8
b and 11b are electrically connected.

On the insulating film 12 on the outermost side of the chip region A, Al-
A pad 15 made of Si-Cu or the like is formed. Although not shown, the pad 15 is made of gold (A) after the dicing process.
u) and the like are connected to the internal leads of the lead frame via bonding wires. The pad 15 is patterned at the same time as the formation of the wiring 14a.

Further, on the main surface of the wafer 1 in the chip area A,
Except for the pad 15 mentioned above, P-
Protective film 16a made of SiN, etc., protective film made of polyimide etc., which is less likely to crack due to heat treatment and mechanical stress
16b are sequentially applied.

On the other hand, in the wafer 1 in the scribing region B, on the n-wafer 4b and the p-well 6b surrounded by the field oxide film 3, dummy pMOSs 2a and nM
OS2b is formed respectively.

The dummy pMOS 2a is, for example, a MOS for measuring the V _th of the pMOS 5 in the chip region A, and is formed in the source region 17a and the drain region 17b formed in the upper layer of the n-well 4b, and in the gate oxide film 9c. Polycide gate electrode
10c.

Further, the dummy nMOS 2b is, for example, in the chip area A.
This is a MOS for measuring _Vth of nMOS7, and is a source region 18a and a drain region 18b formed in an upper layer of p well 6b.
And a gate electrode 10d having a polycide structure formed on the gate oxide film 9d.

The above-described insulating film 12 is applied to the dummy MOS2 so as to cover the dummy MOS2. In a part of the insulating film 12, source regions 17a, 18a and a drain region 17 of the dummy MOS2 are formed.
Contact holes 13 reaching b and 18b are formed. Then, the wiring 14b is formed through the contact hole 13.
And the source regions 17a, 18a and the wiring 14c and the drain region 17b,
18b are electrically connected. The wirings 14b and 14c are made of, for example, Al-Si-Cu, and are patterned at the same time as the wiring 14a.

In the wafer 1 of this embodiment, as shown in FIG. 1 and FIG. 2, a part of the wirings 14b and 14b connected to the source regions 17a and 18a of the dummy MOS2 is partially connected to the gate electrodes 10c and 10d. In the upper layer, it extends from the source side to the drain side to a position covering a part of the drain regions 17b and 18b, and the gate electrode 1
A shield layer (conductor shielding layer) of the dummy MOS 2 is configured as a structure that completely covers 0c, 10d and the source region 17a (18a).

In the scribing region B, the protective films 16a and 16b have been removed, and the wirings 14b and 14c of the dummy MOS 2 are exposed.

The wells 4a and 4a are located below the field oxide film 3.
A channel stopper 19 formed of an impurity layer having the same conductivity type as the impurities b, 6a, and 6b and having a lower impurity concentration than those is formed.

Next, a method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.

First, an nMOS is formed on the p-wells 4a and 4b and the n-wells 6a and 6b surrounded by the field oxide film 3 of the wafer 1 by an ordinary method.
5, pMOS7 and dummy MOS2 are formed. And these
After an insulating film 12 is deposited by a CVD method or the like so as to cover the MOSs 2, 5, 7 and the field oxide film 3, a contact hole 13 is further formed in a predetermined portion of the insulating film 12 (FIG. 4). (A)).

Next, after depositing a metal layer made of Al-Si-Cu or the like on the upper surface of the insulating film 12 by a sputtering method or the like, this metal layer is patterned by resist etching using a glass mask, and the wirings 14a to 14c And the pads 15 are patterned.

At this time, a part of the wiring 14b connected to the source regions 17a, 18a of the dummy MOS 2 in the scribing region B is replaced with the source region 17a in the upper layer of the gate electrodes 10c, 10d.
A pattern is formed so as to extend to a position covering the entire surfaces of the drain regions 17b and 18b and the drain regions 17b and 18b (see FIG. 2).

Then, after the wafer 1 is put into, for example, a hydrogen atmosphere and subjected to an annealing process, _Vth of the dummy MOS 2 is measured (FIG. 4B).

Next, a P-SiN film is deposited on the main surface of the wafer 1 by a plasma CVD method or the like, and after forming a protective film 16a, a polyimide solution is further applied on the upper surface thereof by a spinner coating method or the like. Baking is performed at 400 ° C. to form a protective film 16b (FIG. 4C).

Thereafter, for example, a negative resist 20 is uniformly applied on the upper surface of the protective film 16b, and then a resist pattern is formed using a glass mask (not shown). (FIG. 4 (d)).

Then, using the resist pattern as a mask, a portion of the protective film 16b that is not covered with the resist 20 is removed with a wet etching solution such as hydrazine (fourth).
Figure (e).

Further, using the resist pattern and the protective film 16b as masks, the protective film 16 in the scribing region B is used.
a is removed by, for example, a plasma dry etching method. At this time, the dummy MOS 2 is protected from charged particles such as ions and free electrons in the plasma by the shield layer which is a part of the wiring 14b. Further, the charges generated by the charged particles are removed to the source side via the shield layer (FIG. 4 (f)).

Thereafter, the wafer 1 is put into, for example, oxygen plasma, and the unnecessary resist 20 is removed by ashing. At this time, the influence of the charged particles on the dummy MOS 2 is prevented by the shield layer of the wiring 14b.

Then, although not shown, after polishing the back surface of the wafer 1, _Vth of the dummy MOS2 is measured. V measured at this time
_th is the dummy MOS2 measured after the above annealing treatment.
_Does not fluctuate significantly with respect to V _th , the reliability of the measured V _th is improved.

Thus, the wafer 1 shown in FIG. 1 is manufactured.

As described above, according to the present embodiment, for example, when the protective film 16a is removed by dry etching in the scribing region B, or when the resist 20 applied to remove the protective films 16a and 16b is removed by ashing in plasma. Meanwhile, the dummy MOS 2 is protected from charged particles in the plasma by a shield layer that is a part of the wiring 14b,
Since the generated charges and the like are removed to the source side via the shield layer, a large change in V _th of the dummy MOS 2 supposed to be caused by the charged particles is prevented.

As a result, the reliability of the measured value of _{Vth in} the dummy MOS 2 is improved, so that a highly reliable semiconductor device can be provided.

As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments, and it can be said that various modifications can be made without departing from the gist of the invention. Not even.

For example, in the above embodiment, P
Has been described the case of forming the protective film made of -SiN, it is not limited thereto, and can be variously changed, plasma silicon oxide (P-SiO ₂₎ film, phosphosilicate glass (PSG) film, silane It may be a film or the like.

Further, in the above-described embodiment, the case where the surface protection film made of polyimide is formed on the uppermost layer of the wafer 1 has been described. However, the present invention is not limited to this, and various changes can be made.

In the above description, the invention made by the inventor was mainly applied to a method of manufacturing a semiconductor device having a mask ROM and a semiconductor wafer used for the method, which are the fields of application that served as the background. Instead, the present invention can be applied to various methods, for example, a method of manufacturing another semiconductor device having a logic circuit such as a gate array and a semiconductor wafer used for the method.

〔The invention's effect〕

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

That is, a method of manufacturing a semiconductor device having a dummy MOS transistor for measuring a threshold voltage in a scribing region at a semiconductor wafer stage, wherein the dummy MO
After forming a conductor shielding layer connected to the source electrode of the dummy MOS transistor on the upper layer of the S transistor, a plurality of surface protection films are formed on the surface of the semiconductor wafer, and the plurality of surface protection films in the scribing region are further removed. When the protective film in the scribing area is removed by dry etching, or when the resist film applied to remove the protective film is removed in plasma, for example, a dummy is formed by the conductor shielding layer.
MOS is protected from charged particles in the plasma,
Since the generated charges and the like are removed to the source side via the conductor shielding layer, a large change in _Vth of the dummy MOS, which is assumed to be caused by the charged particles, is prevented.

As a result, the reliability of the measured value of the dummy MOS is improved, so that a highly reliable semiconductor device can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view of a principal part of a semiconductor wafer used in a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is an enlarged plan view of a dummy MOS in a scribing region of the semiconductor wafer. 4 (a) to 4 (f) are cross-sectional views of a main part of the semiconductor wafer showing a method of manufacturing the semiconductor device. 1 ... Semiconductor wafer, 2 ... Dummy MOS, 2a ... Dummy p
MOS, 2b: dummy nMOS, 3: field oxide film, 4a,
4b ... n well, 5 ... pMOS, 6a, 6b ... p well, 7
... nMOS, 8a, 11a ... source region, 8b, 11b ... drain region, 9a to 9d ... gate oxide film, 10a to 10d ... gate electrode, 12 ... insulating film, 13 ... contact hole, 14a , 14c
... wiring, 14b ... wiring (conductor shielding layer), 15 ... bonding pad, 16a, 16b ... protective film, 17a, 18a ... source region, 17b, 18b ... drain region, 19 ... channel stopper, 20: resist, A: chip area, B: scribing area.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-292952 (JP, A) JP-A-56-133871 (JP, A) JP-A-58-9359 (JP, A) 53452 (JP, A) Actually open Showa 64-5450 (JP, U)

Claims (2)

(57) [Claims] 1. A method of manufacturing a semiconductor device comprising a dummy MOS transistor for measuring a threshold voltage in a scribing region at a stage of a semiconductor wafer, the semiconductor device being connected to a source region of the dummy MOS transistor above the dummy MOS transistor. Forming a plurality of surface protection films on the surface of the semiconductor wafer after forming the conductive shielding layer, and removing the plurality of surface protection films in the scribing region. . 2. A semiconductor wafer used in a method of manufacturing a semiconductor device having a dummy MOS transistor for measuring a threshold voltage in a scribing region at a stage of a semiconductor wafer, wherein a surface protective film in the scribing region is removed. And a semiconductor shielding layer connected to a source region of the dummy MOS transistor on an upper layer of the dummy MOS transistor for measuring a threshold voltage formed in the region.