JPS5830146A - Manufacture of mis type semiconductor device - Google Patents

Abstract

PURPOSE:To prevent gate insulating film from breakdown by a method wherein a lower layer wiring to be connected to the gate remains connected to an Si substrate for the escape of charges parasitic on the lower layer wiring until the completion of the upper layer wiring, in a multilayer wiring building process. CONSTITUTION:A field oxide film 12, oxide thin filsm 15 and 15', polycrystalline Si gate electrode 16 are formed on a P<-> type Si substrate 11, and are activated by the forming of N layers 18a, 18b, and 19 by P ion implantation. The entire surface is then covered with a PSG layer 17 wherein windows 20 and 21 are provided, which is followed by the formation of an Al-made source/drain wiring (not illustrated), gate wiring 22, a branch wiring 22' between the gate electrode 16 and the N layer 19. Next, a coating of a PSG layer 23 is applied, wherein windows 24 and 25 are provided to be deposited with an Al layer 27'. Then a resist mask 26 is provided for the formation of an upper wiring 27, which is followed by the sectioning by etching of the branch wiring 22'. In this construction, the lower layer gate wiring 22 remains connected to the substrate 11 via a reverse direction junction between the layer 19 and the substrate 11 until the comletion of the upper wiring 27 to be connected thereto, which allows the high potential charges accumulated in the process of work to escape to the substrate 11 via said junction, thereby preventing the gate oxide film 15 from breakdown.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an MIB-type semiconductor device, particularly MII11! having a multilayer wiring structure. Semiconductor device manufacturing method KW Sui・Multilayer structure OMIIIm! When manufacturing semiconductor devices,
In the conventional O manufacturing method, at the stage of the multilayer interconnection formation process, the lower layer interconnections connected to the gates of the semiconductor element become electrically loose (1i (7 rate leads)). For example, when a connecting window tube is formed on an interlayer insulating film by a dry etching method such as reactive ion etching, the previous underlying layer Iak electric current is accumulated due to the impact of ions or radicals. The lower layer wiring voltage bV.

8- If the withstand voltage of the gate insulating film is increased to more than mg, a discharge occurs through the gate insulating metal and the element is destroyed. In the m formation process @, the lower layer wiring that is connected to the semiconductor substrate is electrically connected to the semiconductor substrate at the neck where the upper layer wiring 0 connection is completed, and the parasitic charges in the lower layer arrangement 11 are not released to the semiconductor substrate. 5 MIEN semiconductor device manufacturing method 1 including means
The present invention is a method for manufacturing MIam semiconductor devices, in which the lower layer wiring is connected! One end of I is electrically connected to the semiconductor substrate, and an interlayer insulating film is formed on the lower layer wiring to expose a region where the lower layer wiring connects with the upper layer wiring. 10th@- and the one end N
Form an upper wiring material layer on the glabellar insulating film, selectively etch the upper wiring material layer, and then expose the upper wiring material layer on the layer barrier rim film. After forming the upper layer wiring that connects the lower layer wiring #Ir in the window 1, the area 0 exposed in the interlayer insulation @V second window 1
The present invention is characterized by a step of selectively etching and removing the lower layer wiring fIB and cutting the lower layer wiring connected to the gate electrode from one end where it is integrally connected to the semiconductor substrate.Hereinafter, the present invention t -**For US+, upper schematic diagram for explaining the gist shown in 11iVk-1 Fig. 2 (+1) to (e) Process sectional view of the first embodiment shown in
No. 20 shown in e)! ! A detailed explanation will be given using process cross-sectional views of examples.

In the present invention-O method, as shown in FIG. 1, 07J#x is usually used for the lower layer insulating material provided on the semiconductor substrate on which the gate electrode 1 and the source/drain regions 2 to 2b are formed. 2" Contacts for p 2 bK @t3m, 3b and contact window 5C1 for gate electrode Ml - When forming contact window 5C1 for semiconductor substrate (diffusion region may be formed in the armpit region): 1 contact window 3d together Then, when forming the lower layer wiring (am), source/drain wiring (114m, 4b) and gate wiring (4C) led out from the contact window on the lower layer insulating layer using a normal method, the gate wiring (m4CK branch) is formed. Arrangement I
! 4C/ is provided, and the branch wiring 4CI is connected to the contact window 3.
The semiconductor substrate (or the diffusion region formed in the region) is connected to K through d.The upper and lower layer interconnections tII are then connected to the interlayer insulating film provided on the substrate on which these lower layer wirings are formed. O arrangement to let you do it! I connection window (via hall)
'5 [When forming <, g the above-mentioned goo 1 layer 11 on the interlayer insulating film
An etching window 6 that crosses and exposes a part of the area of the wiring pattern @4C' is also formed, and then an upper wiring material layer is formed on the interlayer insulating film by a normal method, and then a normal method is applied. Selective etching of the upper layer wiring material layer is performed using the etching method to form the upper layer wiring 7 connected to the gate wiring in the wiring connection window 5 on the layer insulation film, and then the etching window 6 of the glabella insulation film is formed. The layout of the gate wiring exposed inside! 14C'
By selectively etching and removing the upper layer arrangement 7 and the connecting tube, the lower layer gate wiring 4c is connected to the semiconductor substrate (or the diffusion region formed in the region) #IC contacts m4d to 41J are removed. Thereafter, an MI8 type semiconductor structure is formed by a conventional method such as formation of a retentive film.

Next, the method of the present invention will be explained using process diagrams for two embodiments. In the embodiment of fusuma 1, the normal type fP is used, and as shown in the second figure), for example, A field oxide M12 is formed on the silicon (Si) substrate 11, a window is formed in the field oxide III 2 to expose the element forming region 13 and a protective connection forming region 14, and then a window is formed in the above region. A gate oxide film 1B and a thin oxide film 15- are formed at the same time, and then a polycrystalline 8i gate electrode 1116 is formed on the gate oxide film ls, and then the gate electrode 16 and the A5 yield are formed as shown in the second MJ(b)f. Using the oxide film 12 as a mask, KN-type impurity ions (for example, phosphorus ions P) are selectively implanted into the substrate 11 surface to activate the ion-implanted regions and protect the element formation region 15KN-type source/drain regions 18!1.18b. A +a connection forming region 14KN+ type diffusion region 19 is formed, and then a lower insulating film 17 made of phosphosilicate glass PSG and I! is formed on the substrate as shown in FIG. 2 (C1), and then a conventional method is used. Then, in the lower insulating film 17, a contact window for the source/drain region 1g!, 18bK (not shown because it is a region other than the deep cross section), a polycrystalline Bi gate electrode 16, and an N1 type diffusion region 19kM is formed.
Contact windows 20 and 21 are formed, and then the lower insulating film is removed by a conventional method. For example, is there a source/drain circuit made of aluminum (A1) on top of 7? 11 (not shown) and an N type diffusion 1 connected to the gate electrode 16 in the contact window 20 and connected to the gate electrode 16 in the contact window 21.
Gate wiring @22 with branch wiring 22' connected to area 19
Next, as shown in the second stage (d), a glabellar insulating film 23 made of PEG or the like is formed on the substrate, and a gate is formed on the interlayer insulating film 23 by a conventional method. A wiring connection window 24 and an etching window (the branch wiring cutting r6) 25 for the wiring connection window 22 are formed. Next, an upper wiring material layer, for example AjlJjl, is deposited directly above the interlayer insulation, and then as shown in FIG. 2(e)! After selectively etching the upper layer layer 27' using the Ic7 autoresist pattern 26 as a mask to form the upper layer 1 wiring 27 connected to the gate wiring 22 at the wiring 4i1 pile window 24, the etching window 2 is then etched.
Gate arrangement consisting of 1 of the area exposed within 5 -〇 Technique arrangement 1
I22' is selectively etched away to form gate interconnection 2.
2 from the N-type diffusion lJ region.

In the 'J4 embodiment described above, the lower layer gate wiring M22 is formed in the N-type diffusion region 19 and the P-type Sl substrate 11 until the upper layer wiring 27 is formed on the lower layer gate wiring 22. Since it is electrically connected to the P-1184 substrate 11 via a reverse junction with a breakdown voltage of about ~30[VJ], the high potential accumulated in the gate interconnection mK during the multilayer wiring formation process is transferred via the junction. In the first embodiment, the P-type Bt substrate KN N diffusion is maintained so that the Sigut oxide JI115 is not destroyed by the parasitic charge. Although the I-contact a region is formed, P-type diffusion may be performed using the 7-type photoresist as a mask.In that case, the gate electrode and the P118j substrate are connected by ohmic contact.Also, an N-type Bt substrate is used. In the case of nine, the diffusion performed in the connection region is possible for both N type and P type.

In the second embodiment, no junction is provided in the electrical connection region between the gate wiring and the substrate (in other words, as shown in Figure 3), for example, P
- A gate oxide film 15 is formed on the element formation region 13 on the surface of the type 8i substrate 11, a thin lA11i conversion film 15' is formed on the protective connection formation region 14, and a field oxide film 12 is formed on other regions. As shown in FIG. 3(b), a photoresist pattern 28 covering the protective connection formation region 14 is formed on the destroyed layer substrate formed by forming the polycrystalline SI gate electrode 16 on the film 15. Selective implantation of impurity ions (for example, phosphorus ions P) is performed, and then, after removing the 7 auto-resist patterns 28, the previous 6[' ion implantation regions are activated, and the Nll source/drain regions 18a,
18 bt is formed, then a lower insulating film 17 is formed on the substrate in the same manner as in the above embodiment, contact windows 20 and 29 for the source/drain regions are completely formed in the lower insulating film 17, and then a lower insulating film 17 is formed on the lower insulating film 17. In addition, a source/drain wiring m (not shown) made of AL and a branch wiring 22' connecting the gate to the gate 16 and to the P-type Si group 111 are provided.
A gate arrangement @221 [forms]. Next, as in the first embodiment, as shown in FIG. 3(d)K, an interlayer insulating film 23 is formed on the substrate, and then the interlayer insulating film 11I! 23!
(Make the wiring connection window 24 and etching window (branch wiring cutting window) 25 + @ or 44- to the gate wiring IIH 22.
Next, an upper layer A1 film is deposited on the interlayer insulating film 23,
Next! As shown in Figure 1 (@) K, the photoresist
Using the pattern 26 as a mask, the upper 1-Aj film 27' is selectively etched to form the gate wiring in the wiring connection window 24.
After forming the upper layer A1 wiring 27 connected to the gate wiring 22, the gate wiring O branch arrangement m22 in the area exposed in the etching window 25 is selectively removed by etching.
Australia Ill with p-type Si group @11! In the 0-UTI example in which the gate wiring is cut from the wall hole, the connection between the gate wiring O technique M22' and the P-type St substrate 11 is an authentic connection, but in the llk using the N-type Si substrate, the wall hole to lθ~25
A shutoff barrier having a breakdown voltage of about M is formed.And in either case, the charge accumulated in the gate interconnection 4Il by the time the upper layer interconnection is connected to the gate interconnection is transferred through the IiP hole. Since the parasitic charges are released to the substrate, the gate oxide film is not destroyed by the parasitic charges.

Although the first and 20th embodiments have been described above, the present invention is not limited to the 84 substrates and the Al arrangement 1.
A compound semiconductor substrate may be used, and a desired O metal such as titanium (Ti) or molybdenum (MO) can be used as the interconnection material.

It goes without saying that it can also be used for complementary MIt semiconductor devices.

As explained above, according to the present invention, the multilayer wiring structure t)
When manufacturing MIS type semiconductor mounting, multilayer wiring forming process 8
In No. 1, the gate insulating film is not destroyed by charges accumulated in the lower wiring connected to the gate electrode, so the manufacturing yield tb is improved. In addition, in the method of the present invention, the base and O connection regions in the lower layer wiring for K connection are finally cut off from the gate wiring, so the wiring density does not increase, and therefore the element O operation speed decreases. There's nothing to do

[Brief explanation of drawings]

11th garden is method O1 of the present invention! Top view diagram for explanation--＠
211U(a) to M(e) are process cross-sectional views of the third embodiment, and Figures 211U(a) to 3(e) are process cross-sectional views of the third embodiment. -12ae2b are source/drain regions, 3L 3b, 3c, 3d are contact windows,
4 me 4 b is source/drain wiring %4C is goo) arrangement! s4"a goo) layout AILO branch wiring, 5 is a wiring connection window (via hole), 6 is an etching window, 7 is an upper layer wiring%11 is a P1 silicon substrate, 12 is a field oxide film, 13 is an element formation area, 14 15 - Thin oxide film, 16 - polycrystalline silicon gate electrode 21. 29 is contact window, 2
2 is a gate wiring, 22' is a branch wiring, 23 is an interlayer insulating film, 24 is a wiring connection window, 25 is an etching window (branch wiring cutting window), 26. 28 is a 7+ resist pattern, 27
' indicates the upper layer aluminium film, and 27 indicates the upper layer aluminum wiring.

Claims (1)

[Claims] Gate power 1lkK enemy wire lower layer arrangement! One end of the IO is electrically connected to the semiconductor substrate by Km, an interlayer insulating film is formed on the lower layer wiring, and a region connecting the previous lower layer MO upper layer wiring and CLL is exposed on the interlayer insulating film. 10 windows and a 20th window tube exposed across the area tube up to the one end mK are formed, an upper wiring material layer is formed on the interlayer insulating film, and the upper wiring material layer is selectively etched to form an interlayer insulating film. Above said 10th
A region O exposed within the 20th window of the interlayer insulation IIO after forming the upper layer wiring Km connected to the lower layer wiring in the window.
Preparation of MI811 semiconductor device characterized by comprising a step of selectively etching away the lower layer interconnection and cutting off the lower layer interconnection II connected to the gate electrode 1 from one end electrically connected to the semiconductor substrate. Manufacturing method 0