JPS6246026B2 - - Google Patents
Info
- Publication number
- JPS6246026B2 JPS6246026B2 JP4220382A JP4220382A JPS6246026B2 JP S6246026 B2 JPS6246026 B2 JP S6246026B2 JP 4220382 A JP4220382 A JP 4220382A JP 4220382 A JP4220382 A JP 4220382A JP S6246026 B2 JPS6246026 B2 JP S6246026B2
- Authority
- JP
- Japan
- Prior art keywords
- processor
- data
- memory
- processors
- program
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4220382A JPS58159168A (ja) | 1982-03-17 | 1982-03-17 | 並列処理方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4220382A JPS58159168A (ja) | 1982-03-17 | 1982-03-17 | 並列処理方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58159168A JPS58159168A (ja) | 1983-09-21 |
| JPS6246026B2 true JPS6246026B2 (enrdf_load_stackoverflow) | 1987-09-30 |
Family
ID=12629447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4220382A Granted JPS58159168A (ja) | 1982-03-17 | 1982-03-17 | 並列処理方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58159168A (enrdf_load_stackoverflow) |
-
1982
- 1982-03-17 JP JP4220382A patent/JPS58159168A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58159168A (ja) | 1983-09-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5920714A (en) | System and method for distributed multiprocessor communications | |
| US4809169A (en) | Parallel, multiple coprocessor computer architecture having plural execution modes | |
| US5490253A (en) | Multiprocessor system using odd/even data buses with a timeshared address bus | |
| US4951193A (en) | Parallel computer with distributed shared memories and distributed task activating circuits | |
| AU714681B2 (en) | Parallel processor with redundancy of processor pairs | |
| EP0260862A2 (en) | Move-out queue buffer | |
| US3447135A (en) | Peripheral data exchange | |
| JPH04348451A (ja) | 並列計算機 | |
| JPH04246745A (ja) | 情報処理装置及びその方法 | |
| EP0480858A2 (en) | Hardware primary directory lock | |
| US3728682A (en) | Computer input-output chaining system | |
| JPS6246026B2 (enrdf_load_stackoverflow) | ||
| JPS6259347B2 (enrdf_load_stackoverflow) | ||
| JPS6259345B2 (enrdf_load_stackoverflow) | ||
| JPS6259346B2 (enrdf_load_stackoverflow) | ||
| JPS61136157A (ja) | マルチ・マイクロプロセツサ・モジユ−ル | |
| JPH0215152Y2 (enrdf_load_stackoverflow) | ||
| JP3038257B2 (ja) | 電子計算機 | |
| Ghosal et al. | SHAMP: an experimental shared memory multimicroprocessor system for performance evaluation of parallel algorithms | |
| JPH01263858A (ja) | マルチプロセッサシステム | |
| JPH0340169A (ja) | 多重プロセツサシステムおよび複数の処理装置を制御する方法 | |
| JPH0449723Y2 (enrdf_load_stackoverflow) | ||
| JPH10247182A (ja) | マルチプロセッサシステム | |
| JPS63231668A (ja) | 割込みキユ−制御方式 | |
| JPH0573518A (ja) | メモリマツプドcpuシステム |