JPS6245870U - - Google Patents

Info

Publication number
JPS6245870U
JPS6245870U JP1985130097U JP13009785U JPS6245870U JP S6245870 U JPS6245870 U JP S6245870U JP 1985130097 U JP1985130097 U JP 1985130097U JP 13009785 U JP13009785 U JP 13009785U JP S6245870 U JPS6245870 U JP S6245870U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit element
printed wiring
wiring board
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1985130097U
Other languages
English (en)
Other versions
JPH0331092Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985130097U priority Critical patent/JPH0331092Y2/ja
Publication of JPS6245870U publication Critical patent/JPS6245870U/ja
Application granted granted Critical
Publication of JPH0331092Y2 publication Critical patent/JPH0331092Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10156—Shape being other than a cuboid at the periphery

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案で用いる集積回路素子の具体例
を示す構成説明図、第２図は本考案で用いるプリ
ント配線板の具体例を示す構成説明図、第３図は
集積回路素子をプリント配線板に取り付けた状態
の一例を示す断面図、第４図は集積回路素子の一
例を示す構成説明図、第５図は従来の取付機構の
一例を示す構成説明図である。 １０……集積回路素子、２０……プリント配線
板、３０……金属板、４０……絶縁シート。

Claims (1)

    【実用新案登録請求の範囲】
  1. 一方の面から側面にかけて複数の接続パターン
    が形成され他方の面には絶縁基材が設けられた集
    積回路素子と、この集積回路素子を嵌め合わせる
    ための開口部が設けられこの開口部の周囲には集
    積回路素子の所定の接続パターンと接続される複
    数の配線パターンが形成されたプリント配線板と
    、このプリント配線板の一方の面に取り付けられ
    た金属板とからなり、前記集積回路素子はその絶
    縁部材面が金属板と接触するようにしてプリント
    配線板の開口部に嵌め合わされ、集積回路素子の
    所定の接続パターンとプリント配線板の所定の配
    線パターンとが接続部材で接続されたことを特徴
    とする集積回路素子取付機構。
JP1985130097U 1985-08-27 1985-08-27 Expired JPH0331092Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985130097U JPH0331092Y2 (ja) 1985-08-27 1985-08-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985130097U JPH0331092Y2 (ja) 1985-08-27 1985-08-27

Publications (2)

Publication Number Publication Date
JPS6245870U true JPS6245870U (ja) 1987-03-19
JPH0331092Y2 JPH0331092Y2 (ja) 1991-07-01

Family

ID=31027269

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985130097U Expired JPH0331092Y2 (ja) 1985-08-27 1985-08-27

Country Status (1)

Country Link
JP (1) JPH0331092Y2 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07170050A (ja) * 1993-12-15 1995-07-04 Nec Corp 半導体装置
JPH07321439A (ja) * 1994-05-27 1995-12-08 O K Print:Kk メモリ装置用部品取付板
KR20210090167A (ko) 2018-09-20 2021-07-19 뉴로슈티컬즈 인크. 의료용 튜브 위치 확인 시스템

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07170050A (ja) * 1993-12-15 1995-07-04 Nec Corp 半導体装置
JPH07321439A (ja) * 1994-05-27 1995-12-08 O K Print:Kk メモリ装置用部品取付板
KR20210090167A (ko) 2018-09-20 2021-07-19 뉴로슈티컬즈 인크. 의료용 튜브 위치 확인 시스템

Also Published As

Publication number Publication date
JPH0331092Y2 (ja) 1991-07-01

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