JPS6245163A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To predetermine the resistance value of a resistance element without increasing a layout area so much by a method wherein the conductive impurity concentration of a diffused layer which composes the resistance element is variably controlled independently on the conductive impurity concentration of a diffused layer which composes an active element. CONSTITUTION:After an n<-> type epitaxial layer 2 is formed on a p<-> type Si substrate 1, a groove 9, which is to be a part of an isolation region, is formed. Then, a p-type conductive impurity is selectively diffused to form a base region 61 of an n-p-n bipolar transistor, a diffused layer 62 which is to be one resistance region and a diffused layer 64 which is to be an isolation layer 64 are simultaneously formed. Then, a diffused layer 63 which is to be the other resistance element region is formed by a separated independent process. Then, an n-type conductive impurity is selectively diffused to form an emitter region and collector region (not shown) and electrodes (not shown) are formed. With this constitution, the resistance value of a resistance element in the IC can be arbitrarily predetermined without increasing a layout area significantly.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit technology and a technology that is particularly effective when applied to a semiconductor integrated circuit device having a resistive element. It is about effective techniques.

[Background technology]

For example, in a linear semiconductor integrated circuit device that handles analog signals, it is difficult to assemble the circuit inside the semiconductor integrated circuit device using only active elements such as bipolar transistors, and most of them use passive elements such as resistors. have it in some form.

For example, FIG. 2 shows the main parts of a differential amplifier circuit often used in this type of linear semiconductor integrated circuit device. The differential amplifier circuit shown in the figure consists of a differential pair of bipolar transistors Q2 and Q3, and a collector load resistance element R.
2, R3, a bipolar transistor Q1 forming a constant current circuit, a resistor element R1, etc. +
Vc is the positive power supply, -Vc is the negative power supply, VC3 is the pace control voltage of the bipolar transistor Ql, Vin 1
．． Vin2 represents a differential input voltage, and Vout represents a differential output voltage.

Here, the operating characteristics and operating accuracy of the differential amplifier circuit as shown in FIG.
It largely depends on the resistance values of R2 and R3 and their accuracy.

For example, in order to increase the amplification gain (voltage gain) of the differential amplifier circuit, the resistance values of the load resistors R2 and 1t3 must be increased, and the resistance value of the resistive element R1 of the constant current circuit must be set low. Must be. Furthermore, in order to increase the operating speed, it is necessary to set the resistance values of the resistive elements R1, R2, and R3 to a relatively low value. On the other hand, if it is desired to particularly reduce the power consumption of the circuit, the resistance value of each resistive element R1 must be set to a high value.

In such VC, linear semiconductor integrated circuit devices, etc., the resistance value of the resistance element used therein has a very important meaning. By selecting the resistance value of the resistor element, various operating characteristics of the circuit can be set.
It was formed using a diffusion layer formed at the same time as the base region of the transistor. For example, in order to form an active element such as a bipolar transistor, a diffusion layer containing conductive impurities at a predetermined concentration is selectively formed. This diffusion layer has a constant area resistivity (sheet resistance) ρS. Therefore, by selecting the layout shape of the diffusion layer, that is, its length and width, a resistor element having a predetermined resistance value can be formed in a semiconductor integrated circuit device.

Here, in the past, for example, the resistivity ρS of the diffusion layer forming the base region of a bipolar transistor is ρS=
It was fixed at a constant value of 200 Ω/mouth or ρs = I R0/mouth. This is to optimize the characteristics of active elements such as bipolar transistors. Therefore, when using this diffusion layer to obtain a resistor element with a predetermined resistance value, the concentration of the diffusion layer is fixed as is, and only the layout shape of the diffusion layer, that is, its length and width, is manipulated. Ta.

However, if one attempts to set the resistance values of resistive elements such as R1 and R2 in the differential amplifier circuit of FIG. 2 to a particularly high or particularly low value simply by manipulating the layout shape of the diffusion layer, the layout The shape is abnormally large compared to that of the active element, and furthermore, the shape is irregular and extremely long in either the width direction or the length direction. For example, to obtain a low resistance value, a large number of resistive elements must be connected in parallel.

This requires an irregularly shaped layout space that is abnormally long in the width direction. Furthermore, in order to obtain a high resistance value, a very long layout shape is required.

For this reason, a large layout area is occupied within the semiconductor chip by the resistive elements alone, and even if active elements are made smaller, the actual degree of integration cannot be further improved. Also,
The inventors have found that when building a circuit that requires a particularly low resistance value or a particularly high resistance value, there is a problem in that only the resistance element must be externally attached. 1. Regarding resistive elements formed in semiconductor integrated circuit devices, for example, see "Integrated Circuit Optics (1)" published by Corona Co., Ltd., co-authored by Hisayoshi Yanai and Minoru Nagata, published on April 5, 1978, It is described on pages 121-130 (monolithic resistance).

[Purpose of the invention]

An object of the present invention is to reduce the resistance value of a resistive element formed in a semiconductor integrated circuit device by significantly reducing the layout area by using a simple configuration that only slightly changes the operation in a part of the manufacturing process of the semiconductor integrated circuit device. This makes it possible to set the IJ near circuit to a significantly lower or higher value without any significant increase, thereby increasing the actual degree of integration. The object of the present invention is to provide a technology that enables assembly only within a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief description of typical inventions disclosed in this application is as follows.

In other words, by controlling the conductive impurity concentration of the diffusion layer that forms the resistive element separately from the conductive impurity concentration of the diffusion layer that forms the active element, we can optimize customer needs by using the ion implantation method in particular. By varying the amount of ion implantation so as to satisfy Allows resistance values to be set significantly lower or higher without significantly increasing layout area;
This not only makes it possible to substantially improve the degree of integration, but also makes it possible to build a +7 near circuit with the desired optimal operating characteristics only within the semiconductor integrated circuit device, without using external resistive elements. It accomplishes its purpose.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or similar parts.

FIGS. 1A to 1F show an embodiment of a method for manufacturing a semiconductor integrated circuit device according to the present invention in the order of its steps.

First, the configuration of its main parts will be explained.

The method shown below is a method for manufacturing a semiconductor integrated circuit device having a resistance element R1゜㇠2 formed by diffusion layers 62 and 63, as shown in the completed state in FIG. The above resistance element R1,
While forming the region I't2, the resistive element R1
, R2 have a predetermined resistance value.
, R2 is characterized in that the concentration of conductive impurities diffused into the regions R2 is variably controlled.

At this time, in the embodiment, as shown in FIG.
63 is formed at the same time as the diffusion layer formed in the region of the active device. At the same time, as shown in FIG. 2D, only the conductive impurity concentration which becomes the diffusion layer of the resistance element R1 whose resistance value is particularly desired to be set 17 is selectively increased.

As described above, by slightly varying the operations in a part of the manufacturing process, the resistance value of resistor element R2 can be set high without significantly increasing the layout area, while the resistance value of resistor element R1 can be set high. can be set significantly lower.

As a result, it is possible to substantially improve the degree of integration, and it is also possible to assemble a linear circuit having desired operating characteristics only within the semiconductor integrated circuit device without using an external resistance element.

Next, each process step shown in FIGS. 1(a-1-f) will be explained.

(a) shows a pre-processed semiconductor substrate. This substrate has an n-type epitaxial layer 2 formed on a p-type silicon semiconductor substrate 1, and an n-type buried layer 3 is formed in the form of an island between the substrate 1 and the epitaxial layer 2 as necessary. has been done. Further, 4 indicates an oxide film, and 5 indicates a nitride film.

(b) shows a state in which a groove 9 forming a part of the isolation region is formed. This groove 9 is formed by anisotropic etching using an alkaline solution, for example, using the oxide film 4 and the nitride film 5 as masks. By forming the element isolation region using this R9, the width of the isolation region can be narrowed, thereby increasing the degree of integration of the element formation.

(C) shows a step of selectively diffusing a p4 type impurity such as boron (B). In this step, a predetermined amount of impurity is deposited by a deposition method, and then diffused by heating. Through this diffusion process, n
A base region 61 of a pn bipolar transistor, a diffusion layer 62° serving as a resistive element region, and a diffusion layer 64 serving as an isolation region are formed at the same time.

In this step (d), the diffusion layer 63 which becomes the region of the resistance element R2 described above is formed in an independent process using an ion implantation method so that the resistance element R2 has a predetermined low resistance value. In this case, the resistance value is adjusted by controlling the amount of ion implantation.

(e) shows a step of selectively diffusing n-conductivity type impurities such as phosphorus (P). This forms an n+ type emitter region 61 and an n+ type collector current collection region 62 of an npn bipolar transistor.

(f) shows the completed state with the electrode 8 formed. R1 represents a resistive element having a predetermined low resistance value, R2 represents a resistive element having a predetermined high resistance value, and Ql represents an npn bipolar transistor.

Further, C indicates a collector, B indicates a base, and E indicates an emitter.

In the manner described above, a semiconductor integrated circuit device having resistance elements RIJ2 each having an optimum resistance value set is formed.

Here, in the step (C), by setting the impurity concentration of the p-conductivity type impurity diffusion layer (61, 62, 63, 64) in accordance with the resistance value of the resistance element R2,
The impurity concentration in the pace region 61 of the -RA transistor Q1 may deviate slightly from the optimum concentration, which may cause its operating characteristics to change slightly. However, as mentioned above, the operating characteristics and operating accuracy of differential amplifier circuits etc. (well, most of them depend on the resistance value of the resistor element,
Among these resistance layers, those that particularly require adjustment (
For example, since it is formed in an independent process using implantation, it is hardly affected by the characteristics of bipolar transistors, which are active elements. Therefore, even if the operating characteristics of the bipolar transistor Q1, for example (Cf current amplification factor) were to change slightly, there is almost no concern that this would affect the operation of the actual circuit.In fact, By setting the resistance value of resistor element R2 with high precision, the operating characteristics and operating accuracy of the actual circuit can be greatly improved.Therefore, circuits such as A-D converters can also be formed with high precision. i.e. A/D
By changing the resistance value using a converter, etc., the speed and power consumption can be easily set according to the application of the product. In other words, since speed and power consumption have the relationship shown in FIG. 3, it is possible to set the optimum point by selecting the resistance value K.

FIG. 4 shows an example of the layout of the IC chip 90 using the present invention.

In the fixed resistance region, a resistance region with a fixed pS is formed by using the formation process of other active elements to standardize the process and achieve a balance between power consumption and high speed as in differential amplifiers and multiplexers. In the extremely important region 110, optimal design is performed in an independent process using implantation.

〔effect〕

(1) The conductive impurity concentration of the diffusion layer forming the resistance element is
Conductive impurities in the diffusion layer forming the active element)! The resistance value of the resistive element formed in the semiconductor integrated circuit device can be changed by varying the resistance value of the resistor element formed in the semiconductor integrated circuit device with a simple configuration that only slightly changes the operation in a part of the manufacturing process of the semiconductor integrated circuit device by performing variable operation separately from the one-time operation. , can be set significantly lower or higher without significantly increasing layout area), which allows for a substantial increase in integration density and the ability to externally integrate linear circuits with desired operating characteristics. This has the effect that it can be assembled within the semiconductor integrated circuit device without using the resistor element.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the diffusion layers 62 and 63 forming the resistive element region may be n-conductivity type diffusion layers.

[Application field]

When the above invention made by the present inventor is applied to the technology of IJ near semiconductor integrated circuit devices, which is the background field of application, for example, semiconductor integrated circuit devices having differential amplifier circuits, A-D converters, etc. I explained about
The invention is not limited thereto, and can be applied to, for example, technology for high-speed logic semiconductor integrated circuit devices that require resistors with particularly low resistance values in order to increase speed. This is applicable to at least a condition in which a resistance element is provided inside.

[Brief explanation of drawings]

FIGS. 1(a) to 1(f) are diagrams showing, in order of steps, an embodiment of a method for manufacturing a semiconductor integrated circuit device according to the present invention, and FIG. 2 is a diagram showing an example of a circuit to which the present invention is applied. FIG. 3 is a diagram showing the relationship between circuit speed and power consumption when the resistance value of the resistor is changed. FIG. 4 is a layout diagram of an IC showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...p-type silicon semiconductor substrate, 2...n-type bitaxial layer, 3...n+ type buried layer, 61...n
Base region of pn bipolar transistor Ql, R1
゜R2...Resistance element, 62.63...Diffusion layer for forming the resistance element, 90...IC chip. Figure 1 ((Lnra). 3' Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] a step of forming a first resistance layer in the same step as the step of forming an impurity-introduced region constituting an active element; and a step of forming a first resistance layer using an ion implantation method, the sheet resistance of which is different from that of the first resistance layer. 2. A method for manufacturing a semiconductor device, comprising the step of forming a second resistive layer.