JP2007019702A - Level setting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level setting circuit capable of setting a signal at a specified level and outputting it, and reducing a variation in setting level caused by a process variance. <P>SOLUTION: An emitter follower uses a bipolar transistor Q2 having a base for an input and an emitter for an output, wherein a first load resistance 2 connects the base and the emitter of the bipolar transistor Q2, and a second load resistance 3 connects specific potential connected with the collector side of the bipolar transistor Q2 to the base. A switch SW1 is connected to the base of the bipolar transistor Q2 in series. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention generally relates to a level setting circuit, and more specifically, has been improved so that a signal can be set to a predetermined level and output, and variation in setting level due to process variation can be reduced. The present invention relates to a level setting circuit.

  The miniaturization and higher functionality of the manufacturing process of integrated circuits make it possible to lower the power supply voltage. The demand for low power consumption operation of electronic devices is only increasing, and this trend is inevitable. However, lowering the power supply voltage directly leads to a decrease in the voltage margin of the circuit, as symbolized by a malfunction of the circuit caused by a slight power supply fluctuation. Circuit designers are challenged to design a circuit having a predetermined function under the constraint of strict voltage margin.

  A circuit that outputs a signal set to a predetermined level is a function that is generally used to set an input signal of a next-stage circuit to a predetermined level.

  A simple level setting circuit is shown in FIG. This is an emitter follower in which the input signal terminal 11 is connected to the base of the NPN transistor Q12, the output signal terminal 10 and the current source Is12 are connected to the emitter, and the input signal is shifted negatively and output to the emitter. When the current value of the current source Is12 is changed, the base-emitter voltage VBE of the NPN transistor Q12 is changed, and the shift amount of the output signal with respect to the input signal, that is, the set level of the output signal is changed.

  FIG. 9 is an application of the circuit of FIG. 8 as the output of the differential operation circuit. This circuit includes an NPN transistor pair Q11 (Q11a, Q11b) and a current source Is11, the emitters of which are connected in common, and NPN transistors Q12a, Q12b that form an emitter follower at each collector. Also, load resistors 13a and 13b are connected to the collectors of the NPN transistors Q11a and Q11b, respectively, and the load resistors 13a and 13b are connected in common at the other end of the load resistor 14 whose one end is connected to the power supply voltage. ing. Output signal terminals 10a and 10b are connected to respective emitters of NPN transistors Q12a and Q12b. Reference numerals 11a and 11b denote input signal terminals.

  Based on the same principle as described above, the shift amount of the output signal with respect to the differential load voltage, that is, the set level of the output signal changes depending on the current values of the current sources Is12a and Is12b. Further, when the resistance values of the load resistors 13a, 13b, and 14 are changed, the amplitude and set level of the output signal are changed.

  FIG. 10 shows a circuit disclosed in Patent Document 1. Three pairs of field effect transistor pairs and current sources having a common source connected to each other, input signal terminal pairs 11a and 11b are connected to the gates of one field effect transistor pair Q11, and output signal terminal pairs 10a and 10b are connected to the drains. Has been. In one transistor Q21a, Q22a of the field effect transistor pair Q21, Q22, the same control signal terminal 20a is connected to the gate, and the output signal terminal 10a and the power supply voltage are connected to the drain, respectively. In the other transistor Q21b, Q22b of the field effect transistor pair Q21, Q22, the same control signal terminal 20b is connected to the gate, and the power supply voltage and the output signal terminal 10b are connected to the drain, respectively. The output signal terminals 10a and 10b are respectively connected to the other ends of the load resistors 13a and 13b, each having a power supply voltage. Is11, 21, 22 are current sources.

  When the control signal is changed, the current value of the current flowing through the field effect transistor pair Q21 and Q22, that is, the current value of the current flowing through the load resistors 13a and 13b is changed, and the level of the differential load voltage, that is, the output voltage is changed. . Furthermore, when the resistance values of the load resistors 13a and 13b and the current value of the current source Is11 are changed, the amplitude and level of the output signal change.

Japanese Patent Laid-Open No. 9-18329

  In general, in an integrated circuit manufacturing process, variations (hereinafter referred to as process variations) due to non-uniformity in doping profiles, dopant diffusion distances, alignment accuracy, and the like occur. The process variation particularly gives a large variation in the threshold value of the field effect transistor and the absolute value of the resistance which is a passive element.

  In the conventional circuit exemplified above, there are the following problems in setting and outputting a signal at a predetermined level.

  When a diffused resistor or a polycrystalline silicon resistor is used as the load resistor, the absolute value of the resistor is generally given a variation of 10% or more (hereinafter, particularly resistance variation) due to process variations. For this reason, in the conventional circuit in which the output level is determined by the absolute value of the resistance at least between wafers and lots, an unintended large variation occurs in the output level. In particular, when the next-stage circuit is a circuit with a small operating input voltage range and a small voltage margin, a slight deviation in the output signal level can be fatal and cause malfunction of the circuit.

  On the other hand, when a field effect transistor that operates in the triode region is used as the load resistance, the set level of the output signal varies greatly due to threshold variations caused by process variations. When a bipolar transistor having a base and a collector connected as a load resistance is used, the variation in setting level due to process variations is relatively small, but the voltage drop between the load resistors is about VBE (generally 0.7 V or more), and a predetermined value. It cannot be said that the load resistance is suitable for low voltage operation.

  The level setting circuit of FIG. 8 that does not require a load resistance is not suitable for (A) differential signal level setting, and (B) the output signal setting level that changes depending on the current value of the current source is not sufficiently high. There is. On the other hand, in the devices of FIGS. 9 and 10, there is a problem of variation in the setting level of the output signal due to process variation as described above. In particular, the device of FIG. 10 has (A) a large number of elements and large power consumption. (B) There is another problem that a highly accurate control signal that compensates for process variations is required.

  As described above, (A) applicable to differential signals, (B) output level settable range is relatively large, (C) variation in setting level due to process variation is small, and (D) the number of constituent elements is small. The level setting circuit is suitable for low voltage operation and low power consumption operation.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a level setting circuit capable of setting a signal to a predetermined level and outputting it.

  Another object of the present invention is to provide a level setting circuit suitable for low voltage operation and low power consumption operation.

  Another object of the present invention is to provide a level setting circuit that can also be applied to differential signals.

  Another object of the present invention is to provide a level setting circuit having a relatively large output level setting range.

  Another object of the present invention is to provide a level setting circuit in which variations in setting levels due to process variations are small.

  Another object of the present invention is to provide a level setting circuit having a small number of elements.

  According to the level setting circuit of the present invention, in an emitter follower using a bipolar transistor having a base as an input and an emitter as an output, a first load resistor connecting the base and the emitter, and a predetermined potential connected to the collector side It has the 2nd load resistance which connects the said base, and the switch connected in series to the said base, It is characterized by the above-mentioned.

  According to a preferred embodiment, the switch comprises a switching transistor, and the base of the bipolar transistor is connected to the collector or drain of the switching transistor.

  In this case, it preferably has a third load resistor connecting the collector of the bipolar transistor and the predetermined potential.

  A diode may be provided for connecting the collector of the bipolar transistor and the predetermined potential.

  Further, a diode may be provided that connects the emitter of the bipolar transistor and one end of the first load resistor on the emitter side.

  According to another preferred embodiment, the switch is composed of a pair of first and second switching transistors having emitters or sources connected in common. A pair of the bipolar transistors having the first load resistance and the second load resistance are provided, the base of one bipolar transistor and the collector or drain of the first switch transistor are connected, and the other bipolar transistor is connected. The base of the transistor is connected to the collector or drain of the second switching transistor.

  In this case, it preferably has a pair of third load resistors that connect the collectors of the pair of bipolar transistors and the predetermined potential.

  You may have a pair of diode which connects each collector of said pair of bipolar transistor, and said predetermined potential.

  Moreover, you may have a pair of diode which connects each emitter of a pair of said bipolar transistor, and one end by the side of the emitter of each said 1st load resistance.

  According to the present invention, it is possible to realize a level setting circuit that can be applied to both a single-ended input signal and a differential input signal, has a relatively large output level setting range, and a small setting level variation due to process variations. .

  In addition, according to the present invention, the voltage drop between the load resistors necessary for setting the level of the output signal can be controlled to a predetermined value, and since the number of elements is simple and the configuration is low, low voltage operation and low power consumption are achieved. A level setting circuit suitable for the operation can be realized.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit that briefly shows the configuration of a level setting circuit according to the present invention. The output signal terminal 0 and the current source Is2 are connected to the emitter of the NPN transistor Q2. The first load resistor 2 connects the base and the emitter, the second load resistor 3 connects the power supply potential and the base, and the switch SW1 is connected in series to the base.

  A specific example of the level setting circuit of this embodiment is shown in FIG. As the switch SW1 in the level setting circuit of FIG. 1, a switching transistor Q1 connected in series to the base of the NPN transistor Q2 is used, and the base of the switching transistor Q1 serves as the input signal terminal 1. The switch transistor Q1 may be formed of a bipolar transistor as shown in the figure, or may be formed of a field effect transistor. The operation of the level setting circuit according to the present invention will be described below using the level setting circuit of FIG.

  By changing the current value of the current source Is2, the base-emitter voltage VBE of the NPN transistor Q2 can be changed, and the shift amount of the output signal with respect to the collector potential of the switching transistor Q1 can be changed. However, as described in (B) above, even if the current value of the current source Is2 is greatly changed, the shift amount is at most equivalent to the logarithm of the current change amount, for example, about -1.0V. It is difficult to shift (about 1.2 to 1.5 times -VBE). This means that the settable range of the output level is restricted.

  Here, the resistance value of the first load resistor 2 is r2, and the resistance value of the second load resistor 3 is r3. If the resistance value r2 is made sufficiently high and the current flowing through the first load resistor 2 is set to be sufficiently smaller than the current flowing between the collector and emitter of the NPN transistor Q2, the amount of shift of the on level of the output signal with respect to the power supply voltage Is represented by-(1 + r3 / r2) VBE (quantitative explanation will be described later).

  Therefore, if r3 / r2 is set within a range in which a sufficient voltage is secured so that the current source Is2 does not deviate from the normal operation by using the circuit configuration shown in FIG. The level setting range can be made relatively large.

  The greatest feature of using the circuit configuration of this embodiment is that the shift amount is determined not by the absolute value of the resistance value but by the ratio of the resistance value. That is, even if the resistance value varies by 10% or more due to resistance variation, the shift amount is set to a substantially constant value.

  The variation in the characteristic value of the active element due to the process variation is unavoidable, but in general, the variation in the process causes the characteristic value of the active element constituting the circuit connected before and after the level setting circuit to vary in the same direction. It does not cause a serious situation with respect to variation. At least the variation in the shift amount due to the resistance variation can be extremely reduced, which results in an effect of further suppressing the setting level (unintentional) variation caused by the process variation.

  By the way, although it is assumed that a diffused resistor or a polycrystalline silicon resistor is used as the load resistor, if an unintended parasitic capacitance is added between the base and the emitter of the NPN transistor Q2 in association with this, the capacitance value is increased. It should be noted that there is a possibility that an operation in a predetermined frequency band may not be obtained depending on the size of.

  The above is an explanation of the case where an NPN transistor is used. However, it can be easily understood that the shift amount can be made positive by realizing it using a PNP transistor.

  FIG. 3 is a circuit diagram of a level setting circuit according to the second embodiment. The switch is composed of a pair of first and second switch transistors Q1a and Q1b, in which an emitter (when a bipolar transistor is used) or a source (when a field effect transistor is used) is connected in common. A pair of bipolar transistors Q2a and Q2b having first load resistors 2a and 2b and second load resistors 3a and 3b are provided. The base of one bipolar transistor Q2a is connected to the collector or drain of the first switching transistor Q1a. The base of the other bipolar transistor Q2b is connected to the collector or drain of the second switching transistor Q1b. 1a and 1b are input signal terminals, 0a and 0b are output signal terminals, and Is1, Is2a, and Is2b are current sources.

  As described above, the level setting circuit according to the first embodiment has the switch transistor pair Q1 whose emitters are commonly connected, and the bases of the NPN transistors Q2a and Q2b are respectively connected to the collectors of the switch transistors Q1a and Q1b. A connected configuration may be used. On the other hand, the level setting circuit of the present embodiment can be regarded as an application of the level setting circuit of the first embodiment as the output of the differential operation circuit. The resistance values of the first load resistors 2a and 2b are the same, and the resistance values of the second load resistors 3a and 3b are the same.

  The level setting circuit of the present embodiment is characterized in that it can be applied to differential signals in addition to the same effects as the level setting circuit of the first embodiment.

  Here, in order to compare the differential output operation of the level setting circuit of this embodiment (FIG. 3) and the conventional level setting circuit (FIG. 9), the differential load voltage and the differential output signal voltage in each level setting circuit. FIG. 4 (a) and FIG. 4 (b) respectively show the relationship (only one is displayed).

  As a result of the switching operation by the differential input signal, the difference between the differential load voltage and the differential output signal voltage is VBE. The amplitude of the differential output signal is represented by the product of the resistance values r3 and r13 of the load resistors 3a, 3b, 13a and 13b, and the current values I1 and I11 of the current sources Is1 and Is11, both of which are affected by resistance variations. Receive.

  By the way, in the level setting circuit of FIG. 9, since the ON level of the differential output signal is represented by the product of the resistance value r14 of the load resistor 14 and the current value I11 of the current source Is11, the ON level is affected by the resistance variation. It will be received directly and vary.

  On the other hand, in the level setting circuit of this embodiment, the ON level is the ratio r3 / r2 between the resistance value of the second load resistance pair 3a, 3b and the resistance value of the first load resistance pair 2a, 2b, and the NPN transistor pair. The on-level variation represented by the product of the base-emitter voltage VBE of Q2a and Q2b, that is, the resistance variation, is extremely small.

  Therefore, in the level setting circuit of this embodiment, as a result, the common level of the differential output signal is hardly affected by the resistance variation. In other words, by using the level setting circuit of this embodiment, the settable range of the output level is relatively large, and the variation in the setting level due to the process variation can be reduced.

  FIG. 5 is a circuit diagram of a level setting circuit according to the third embodiment. In the circuit shown in FIG. 5, the same parts as those in the circuit shown in FIG. 3 are denoted by the same reference numerals, and the description thereof will not be repeated. This embodiment is characterized in that third load resistors 5a and 5b are connected between the collectors of the NPN transistors Q2a and Q2b and the power supply voltage.

  In general, the collector current of a bipolar transistor is controlled by a base current and hardly depends on the collector-emitter voltage. However, strictly speaking, the collector current increases as the collector-emitter voltage increases due to the phenomenon that the substantial base width changes due to the base-collector depletion layer generated by the collector voltage. This is called the Early effect.

  Consider a case where the current value I2 of the current sources Is2a and Is2b varies due to process variations. As I2 increases from the design value, the base-emitter voltage increases slightly due to the increase in the collector currents of the NPN transistors Q2a and Q2b, resulting in variations in output level. Here, if the load resistances 5a and 5b exist, the voltage drop between the load resistances increases due to the increase in the collector current, so that the collector voltage is suppressed. Become. That is, the base-emitter voltage VBE of the NPN transistors Q2a and Q2b can be compensated for variations in the current value of the current source.

  Therefore, by using the level setting circuit of the present embodiment, it is possible to further increase the controllability of the output signal setting level.

  In this embodiment, the case where the differential input signal is applied has been exemplified. However, a single end input signal as shown in FIG. 2 may be applied.

  FIG. 6 is a circuit diagram of a level setting circuit according to the fourth embodiment. In the circuit shown in FIG. 6, the same parts as those in the circuit shown in FIG. 2 are denoted by the same reference numerals, and the description thereof will not be repeated. This embodiment is characterized in that one diode 6 is connected between the collector of the NPN transistor Q2 and the power supply voltage. However, the output signal terminal 0 is connected not to the emitter of the NPN transistor Q2, but to the collector.

  Here, if the diode 6 is connected to the base and collector of an NPN transistor having the same physical properties as the NPN transistor Q2, the shift amount of the output signal with respect to the on-level power supply voltage is-(r3 / r2 ) VBE.

  Therefore, if the absolute value of the shift amount is set smaller than VBE, the level setting circuit of the present embodiment may be applied.

  In this embodiment, the case where a single-ended input signal is applied has been illustrated, but a differential input signal as shown in FIG. 3 may be applied.

  FIG. 7 is a circuit diagram of a level setting circuit according to the fifth embodiment. In the circuit shown in FIG. 7, the same parts as those in the circuit shown in FIG. 3 are denoted by the same reference numerals, and the description thereof will not be repeated. This embodiment is characterized in that one diode 7a, 7b is connected between the emitters of the NPN transistors Q2a, Q2b and one end of the first load resistors 2a, 2b on the emitter side.

  Here, if diodes 7a and 7b having NPN transistor bases and collectors connected with the same physical properties as NPN transistors Q2a and Q2b are applied, the shift amount of the output signal with respect to the on-level power supply voltage is-( 2 + r3 / r2) VBE.

  Therefore, if the absolute value of the shift amount is set to be large, the level setting circuit of this embodiment may be applied.

  When the number of diodes to be connected is n, the shift amount is − (1 + n + r3 / r2) VBE in a range in which a sufficient voltage is secured so that the current source Is2 does not deviate from the normal operation.

  In this embodiment, the case where the differential input signal is applied has been exemplified. However, a single end input signal as shown in FIG. 2 may be applied.

  It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  According to the present invention, it is possible to obtain a level setting circuit in which the setting level variation due to process variation is small.

FIG. 3 is a diagram illustrating a configuration of a level setting circuit according to the first embodiment. FIG. 3 is a diagram illustrating a specific configuration of the level setting circuit according to the first embodiment. FIG. 6 is a diagram illustrating a configuration of a level setting circuit according to a second embodiment. It is a figure which shows the relationship between the differential load voltage and output signal voltage in Example 2 and the conventional variable level shift (FIG. 9). FIG. 6 is a circuit diagram of a level setting circuit according to a third embodiment. FIG. 10 is a circuit diagram of a level setting circuit according to a fourth embodiment. FIG. 10 is a circuit diagram of a level setting circuit according to a fifth embodiment; It is a figure which shows the structure of a common emitter follower. It is a figure which shows the structure of the conventional level setting circuit. It is a figure which shows the structure of the other conventional level setting circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 0 Output signal terminal 1 Input signal terminal 2 1st load resistance 3 2nd load resistance 5a, 5b 3rd load resistance 6 Diode 7a, 7b Diode 10 Output signal terminal 11 Input signal terminal 13a, 13b Load resistance 14 Load resistance Q1, Q2 transistor SW1, switch Is1, Is2 current source

Claims (9)

In an emitter follower using a bipolar transistor with the base as input and the emitter as output,
A first load resistor connecting the base and the emitter;
A second load resistor connecting a predetermined potential connected to the collector side and the base;
And a switch connected in series to the base. The switch is composed of a switch transistor,
2. The level setting circuit according to claim 1, wherein a base of the bipolar transistor is connected to a collector or drain of the switching transistor. The switch is composed of a pair of first and second switch transistors having emitters or sources connected in common,
A pair of the bipolar transistors having the first load resistance and the second load resistance are provided,
The base of one bipolar transistor and the collector or drain of the first switch transistor are connected,
2. The level setting circuit according to claim 1, wherein the base of the other bipolar transistor is connected to the collector or drain of the second switch transistor.   3. The level setting circuit according to claim 2, further comprising a third load resistor for connecting the collector of the bipolar transistor and the predetermined potential.   4. The level setting circuit according to claim 3, further comprising a pair of third load resistors that connect the collectors of the pair of bipolar transistors and the predetermined potential.   The level setting circuit according to claim 2, further comprising a diode that connects a collector of the bipolar transistor and the predetermined potential.   4. The level setting circuit according to claim 3, further comprising a pair of diodes for connecting the respective collectors of the pair of bipolar transistors and the predetermined potential.   3. The level setting circuit according to claim 2, further comprising a diode connecting the emitter of the bipolar transistor and one end of the first load resistor on the emitter side. 4. The level setting circuit according to claim 3, further comprising a pair of diodes for connecting each emitter of the pair of bipolar transistors and one end of each first load resistor on the emitter side.

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