JPS6244688B2 - - Google Patents

Info

Publication number
JPS6244688B2
JPS6244688B2 JP54150341A JP15034179A JPS6244688B2 JP S6244688 B2 JPS6244688 B2 JP S6244688B2 JP 54150341 A JP54150341 A JP 54150341A JP 15034179 A JP15034179 A JP 15034179A JP S6244688 B2 JPS6244688 B2 JP S6244688B2
Authority
JP
Japan
Prior art keywords
metallized
ceramic substrate
alignment pattern
semiconductor device
internal lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54150341A
Other languages
Japanese (ja)
Other versions
JPS5673442A (en
Inventor
Shigeru Kubota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP15034179A priority Critical patent/JPS5673442A/en
Publication of JPS5673442A publication Critical patent/JPS5673442A/en
Publication of JPS6244688B2 publication Critical patent/JPS6244688B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 この発明は半導体装置にかかり、特にセラミツ
ク基板上に形成された自動ボンデイングの際に使
用する目合せ用パターンに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to an alignment pattern formed on a ceramic substrate and used in automatic bonding.

従来の半導体装置は、第１図の部分平面図に示
す様に、セラミツク基板１の略中央部に半導体素
子５を設置したキヤビテイ部３、そしてキヤビテ
イ部３の周縁から外方に延びるメタライズド内部
リード２と半導体素子５との間が金属細線４で配
線されている。 As shown in the partial plan view of FIG. 1, a conventional semiconductor device includes a cavity part 3 in which a semiconductor element 5 is installed approximately at the center of a ceramic substrate 1, and a metallized internal lead extending outward from the periphery of the cavity part 3. 2 and the semiconductor element 5 are interconnected by thin metal wires 4.

又、セラミツク基板１上のメタライズド内部リ
ード２の間に、自動ボンデイングの目合せ用パタ
ーン６が形成されている。 Further, an alignment pattern 6 for automatic bonding is formed between the metallized internal leads 2 on the ceramic substrate 1.

第２図は従来の半導体装置の第１図のＸ−
X′断面図であり、セラミツク基板１上のメタラ
イズド内部リード２はタングステンメタライズ層
２′に電気メツキを施したメツキ層２″から形成さ
れている。 Figure 2 shows the conventional semiconductor device at X- in Figure 1.
This is an X' cross-sectional view, and the metallized internal leads 2 on the ceramic substrate 1 are formed from a plating layer 2'' which is obtained by electroplating a tungsten metallized layer 2'.

この様な構造の従来の半導体装置は、目合せ用
パターン６で位置合せを行なうことで、メタライ
ズド内部リード２と半導体素子５との間の金属細
線による自動ボンデイングを行つている。 A conventional semiconductor device having such a structure performs automatic bonding between the metallized internal lead 2 and the semiconductor element 5 using a thin metal wire by performing alignment using the alignment pattern 6.

しかしながら、通常目合せ用パターンは、セラ
ミツク基板上にタングステンメタライズで形成し
た独立パターンであるため、電気的な手段による
金属のメツキは施こされず、タングステンメタラ
イズそのままの金属色を呈している。その為、セ
ラミツク基板が黒色基板の場合は、目合せ用パタ
ーンでの位置合せは光沢の違いによつて容易に行
なうとが出来るが、セラミツク基板が白色基板の
場合は、目合せ用パターンとセラミツク基板との
光沢が類似しているため、位置合せが非常に困難
であつた。 However, since the alignment pattern is usually an independent pattern formed of tungsten metallization on a ceramic substrate, metal plating is not performed by electrical means, and the pattern has the same metallic color as the tungsten metallization. Therefore, if the ceramic substrate is a black substrate, alignment using the alignment pattern can be easily performed due to the difference in gloss, but if the ceramic substrate is a white substrate, alignment using the alignment pattern and the ceramic substrate can be easily performed. Because the gloss was similar to that of the substrate, alignment was extremely difficult.

さらに、目合せ用パターンは、メタライズド内
部リード間に径が約0.1〜0.3mmの大きさで形成さ
れるため、メタライズド内部リードが多数本に増
加した時に、セラミツク基板のサイズが規制され
ている場合、メタライズド内部リード幅を狭くす
るか、又は各々のメタライズド内部リード間隔を
狭くする方法が用いられるが、前者では自動ボン
デイング時の位置精度、後者の場合はメタライズ
ド内部リード間の絶縁抵抗、容量等の問題が生ず
る。 Furthermore, since the alignment pattern is formed with a diameter of approximately 0.1 to 0.3 mm between the metallized internal leads, when the number of metalized internal leads increases and the size of the ceramic substrate is restricted. The method used is to narrow the width of the metallized internal leads or to narrow the spacing between each metallized internal lead, but in the former case, the position accuracy during automatic bonding, and in the latter case, the insulation resistance, capacitance, etc. between the metallized internal leads. A problem arises.

従つて高信頼度の自動ボンデイング可能な半導
体装置を提供することが出来なかつた。 Therefore, it has not been possible to provide a highly reliable semiconductor device that can be automatically bonded.

本発明の目的は、前述した自動ボンデイングを
行なうための目合せ用パターンを改良した半導体
装置を提供するものである。 SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device with an improved alignment pattern for performing the above-mentioned automatic bonding.

本発明の半導体装置は、自動ボンデイングを行
なうための目合せ用パターンが、メタライズド内
部リード上に絶縁材料を用いて形成されたことを
特徴とする。 The semiconductor device of the present invention is characterized in that an alignment pattern for automatic bonding is formed on the metallized internal lead using an insulating material.

次に第３図、第４図、第５図を参照して本発明
の実施例を説明する。 Next, an embodiment of the present invention will be described with reference to FIGS. 3, 4, and 5.

第３図は本発明の半導体装置の一実施例を示す
部分平面図で、セラミツク基板１の略中央部に半
導体素子５を設置したキヤビテイ部３、そしてキ
ヤビテイ部３の周縁から外方に延びるメタライズ
ド内部リード７と半導体素子５との間が金属細線
４で配線されている。又、セラミツク基板１上の
メタライズド内部リード７上のボンデイング領域
となる先端部分以外の部分に自動ボンデイングの
目合せ用パターン８が複数個所形成されている。 FIG. 3 is a partial plan view showing an embodiment of the semiconductor device of the present invention, showing a cavity portion 3 in which a semiconductor element 5 is installed approximately at the center of a ceramic substrate 1, and a metallized portion extending outward from the periphery of the cavity portion 3. The internal lead 7 and the semiconductor element 5 are interconnected by a thin metal wire 4. Further, alignment patterns 8 for automatic bonding are formed at a plurality of locations on the metallized internal lead 7 on the ceramic substrate 1 in a portion other than the tip portion which becomes the bonding region.

第４図は第３図の断面図であり、セラミツク基
板１上のメタライズド内部リードは、タングステ
ンメタライズ層７′を形成した上に、金属細線を
接続するためのボンデイング領域以外の部分に目
合せパターン８として絶縁材料を被覆し、更に目
合せパターン８以外のタングステンメタライズ層
７′上に電気メツキによるメツキ層７″が形成され
ている。 FIG. 4 is a cross-sectional view of FIG. 3, and the metallized internal leads on the ceramic substrate 1 have a tungsten metallized layer 7' formed thereon, and an alignment pattern formed on the part other than the bonding area for connecting thin metal wires. 8 is coated with an insulating material, and a plating layer 7'' is formed by electroplating on the tungsten metallized layer 7' other than the alignment pattern 8.

もう一つの実施例を第５図の断面図で説明する
と、セラミツク基板１上に形成したメタライズド
内部リードは、タングステンメタライズ層７′に
電気メツキを施したメツキ層７″からなり、この
メツキ層７″上の金属細線を接続するボンデイン
グ領域以外の部分に、目合せ用パターン８′が絶
縁材料を用いて複数個所に形成されている。 Another embodiment will be described with reference to the cross-sectional view of FIG. 5. The metallized internal leads formed on the ceramic substrate 1 are made of a plating layer 7'' formed by electroplating a tungsten metallization layer 7'. Alignment patterns 8' are formed at a plurality of locations using an insulating material in a portion other than the bonding area where the thin metal wires on the top are connected.

次に本発明の実施例の製造方法について説明す
る。第４図で示した第一の実施例は、既知である
セラミツク積層型半導体装置の製造方法により、
まずグリーンシート上にタングステン粉末を印刷
法を用いて未焼成の内部リードを形成し、該内部
リード上の金属細線を接続するボンデイング領域
以外の部分に、絶縁材料であるアルミナ粉末等を
被覆した後、各々のグリーンシートを積層及び焼
成してセラミツク基板上のメタライズド内部リー
ド上に目合せ用パターンを形成する。さらに外部
リード等をセラミツク基板に取付けた後、ニツケ
ルメツキ、金メツキを施して半導体装置を製造す
る。 Next, a manufacturing method of an example of the present invention will be explained. The first embodiment shown in FIG. 4 uses a known method for manufacturing a ceramic stacked semiconductor device.
First, unfired internal leads are formed by printing tungsten powder on a green sheet, and the parts of the internal leads other than the bonding area where the thin metal wires are connected are coated with insulating material such as alumina powder. , each green sheet is laminated and fired to form an alignment pattern on the metallized internal leads on the ceramic substrate. Furthermore, after attaching external leads and the like to the ceramic substrate, nickel plating and gold plating are applied to manufacture the semiconductor device.

又、第５図で示した他の実施例は、黒色のポリ
イミド等の樹脂を接着することによつて製造した
ものである。 Further, another embodiment shown in FIG. 5 is manufactured by adhering a resin such as black polyimide.

以上本発明について説明したが、目合せ用パタ
ーンである絶縁材料は、各々のメタライズド内部
リード間にかかる様に帯状に形成しても同様な効
果がある。又この目合せ用パターンは、少なくと
も２本のメタライズド内部リード上に設けておけ
ば、目合せの機能を果すことができる。 Although the present invention has been described above, the same effect can be obtained even if the insulating material serving as the alignment pattern is formed in a band shape so as to span between each metallized internal lead. Further, if this alignment pattern is provided on at least two metallized internal leads, it can perform the alignment function.

この様な構造の半導体装置は、自動ボンデイン
グするための目合せ用パターンがメタライズド内
部リード上に形成されているので、各々のメタラ
イズド内部リードの幅はキヤビテイ部周縁の領域
を目一杯使用することが出来る。さらにメタライ
ズド内部リードのメツキ層は、通常金メツキであ
るから、セラミツク基板が白色基板の場合は、メ
タライズド内部リード上に形成した本発明による
目合せ用パターンを使用すれば良く、又、セラミ
ツク基板が黒色基板の場合は、メタライズド内部
リード上に形成した目合せ用パターンより先端の
ボンデイング領域の金メツキ層を使用すれば自動
ボンデイングは信頼性良く行なうことが出来る。
すなわち、白色のセラミツク基板とメタライズド
内部リード上の目合せ用パターンとの明暗差、或
いは黒色のセラミツク基板とメタライズド内部リ
ード上の目合せ用パターンより先端の金メツキ層
との明暗差を利用することによつて、全自動ボン
デイング方法のパターン認識が容易になり、高品
質で高速の自動ボンデイングが可能となる。 In a semiconductor device having such a structure, an alignment pattern for automatic bonding is formed on the metallized internal leads, so the width of each metallized internal lead can be set to fully utilize the area around the cavity. I can do it. Furthermore, since the plating layer of the metallized internal lead is usually gold plating, if the ceramic substrate is a white substrate, the alignment pattern according to the present invention formed on the metallized internal lead may be used; In the case of a black substrate, automatic bonding can be performed reliably by using a gold plating layer in the bonding area at the tip of the alignment pattern formed on the metallized internal lead.
In other words, the difference in brightness between the white ceramic substrate and the alignment pattern on the metallized internal lead, or the difference in brightness between the black ceramic substrate and the gold plating layer at the tip of the alignment pattern on the metallized internal lead is used. This facilitates pattern recognition in a fully automatic bonding method and enables high-quality, high-speed automatic bonding.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体装置の部分平面図、第２
図は第１図のＸ−X′断面図、第３図は本発明の
半導体装置の一実施例を示す部分平面図、第４図
は第３図のＸ−X′断面図、第５図は本発明の半
導体装置の他の実施例を示す断面図である。 １…セラミツク基板、２…メタライズド内部リ
ード、２′…タングステンメタライズ層、２″…メ
ツキ層、３…キヤビテイ部、４…金属細線、５…
半導体素子、６…目合せ用パターン、７…メタラ
イズド内部リード、７′…タングステンメタライ
ズ層、７″…メツキ層、８，８′…目合せ用パター
ン。 Figure 1 is a partial plan view of a conventional semiconductor device, Figure 2 is a partial plan view of a conventional semiconductor device;
3 is a partial plan view showing an embodiment of the semiconductor device of the present invention, FIG. 4 is a sectional view taken along line XX' in FIG. 3, and FIG. FIG. 3 is a sectional view showing another embodiment of the semiconductor device of the present invention. DESCRIPTION OF SYMBOLS 1... Ceramic substrate, 2... Metallized internal lead, 2'... Tungsten metallized layer, 2''... Plating layer, 3... Cavity part, 4... Metal thin wire, 5...
Semiconductor element, 6... Alignment pattern, 7... Metallized internal lead, 7'... Tungsten metallized layer, 7''... Plating layer, 8, 8'... Alignment pattern.

Claims (1)

【特許請求の範囲】[Claims] １ セラミツク基板上にメタライズド内部リード
を形成した半導体装置において、前記メタライズ
ド内部リード上のボンデイング領域となる先端部
分以外の部分にも絶縁材料を用いた自動ボンデイ
ング用位置合せパターンが形成されていることを
特徴とする半導体装置。1. In a semiconductor device in which a metallized internal lead is formed on a ceramic substrate, an alignment pattern for automatic bonding using an insulating material is also formed on a portion of the metallized internal lead other than the tip portion that becomes the bonding region. Characteristic semiconductor devices.
JP15034179A 1979-11-20 1979-11-20 Semiconductor device Granted JPS5673442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15034179A JPS5673442A (en) 1979-11-20 1979-11-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15034179A JPS5673442A (en) 1979-11-20 1979-11-20 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5673442A JPS5673442A (en) 1981-06-18
JPS6244688B2 true JPS6244688B2 (en) 1987-09-22

Family

ID=15494871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15034179A Granted JPS5673442A (en) 1979-11-20 1979-11-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5673442A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008290314A (en) * 2007-05-23 2008-12-04 Tokuyama Corp Metalized substrate and its manufacturing method

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59215736A (en) * 1983-05-24 1984-12-05 Toshiba Corp Setup of substrate and connection of bonding wire
JPS6130264U (en) * 1984-07-27 1986-02-24 三洋電機株式会社 Light emitting diode for printing

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5279658A (en) * 1975-12-25 1977-07-04 Citizen Watch Co Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5279658A (en) * 1975-12-25 1977-07-04 Citizen Watch Co Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008290314A (en) * 2007-05-23 2008-12-04 Tokuyama Corp Metalized substrate and its manufacturing method

Also Published As

Publication number Publication date
JPS5673442A (en) 1981-06-18

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