JPS6244604Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a switching pulse generation circuit for a stereo demodulation circuit of an FM stereo receiver.

In a switching type stereo demodulation circuit, it is known that in order to obtain left and right channel signals with a high degree of separation, it is necessary to make the pulse width of the switching pulse as narrow as possible and to reduce the flow angle of the switching element.

This invention has a simple circuit configuration and is suitable for integrated circuits.
It is an object of the present invention to provide a switching pulse generation circuit which can narrow the pulse width and obtain stable switching pulses.

The purpose is to use a 19K signal that is phase synchronized with the pilot signal.
The oscillation frequency of the voltage controlled oscillator of the PLL circuit that obtains the Hz signal is set to 152 KHz, and the oscillation frequency of the voltage controlled oscillator is divided to obtain 76 KHz and 38 KHz signals, and the output signal of the voltage controlled oscillator is waveform-shaped. This is achieved by synthesizing the 76KHz signal and the 38KHz signal to obtain a switching pulse, and regulating the synthesis so that the peak point of the subcarrier is included within the switching pulse duration range on the time axis.

The present invention will be explained below with reference to examples.

FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, 1 is a phase comparator that compares the phases of the pilot signal in the composite signal and the output signal of the frequency divider 2, 3 is a low-pass filter that receives the output signal of the phase comparator 1, and 4 is a DC amplifier that amplifies the output signal of the low-pass filter 3, 5 is a voltage controlled oscillator that oscillates a 152KHz output signal controlled by the output voltage of the DC amplifier 4, and 6 is a voltage controlled oscillator that oscillates the output signal of the voltage controlled oscillator 5. 7 is a frequency divider consisting of a flip-flop that divides the frequency of the output signal of frequency divider 6 by 1/2; This is a frequency divider that divides the output signal of the frequency generator 7 by 1/2.

Phase comparator 1, low pass filter 3, DC amplifier 4, voltage controlled oscillator 5, frequency divider 6, 7 and 2
The PLL circuit is configured to compare the phases of the 19 KHz input pilot signal and the 19 KHz signal output from the frequency divider 2, and to control the voltage controlled oscillator 5 based on the error component.

On the other hand, 9 is a waveform shaping circuit which receives the output signal of the voltage controlled oscillator 5, slices it at a predetermined level, and shapes the waveform; the output signal of the waveform shaping circuit 9,
The output of the frequency divider 6 and the output of the frequency divider 7 are input to the NOR gate 10, the output signal of the waveform shaping circuit 9, the output of the frequency divider 6 and the Q output of the frequency divider 7 are input to the NOR gate 11, The configuration is such that switching pulses are obtained from the output terminals of NOR gates 10 and 11.

Now, when the PLL circuit is in the lock state, the voltage controlled oscillator 5 oscillates at 152 KHz, and its output voltage waveform is as shown in FIG. 2a. Therefore, the waveform shaping circuit 9 slices the output voltage of the voltage controlled oscillator 5 shown in FIG. 2a at level L, and outputs an output voltage having a pulse waveform shown in FIG. 2b. Further, the frequency divider 6 is triggered by the output voltage of the voltage controlled oscillator 5, divides the frequency (152KHz) by 1/2, and outputs an output voltage with a pulse waveform of 76KHz as shown in FIG. 2c as a Q output. The second output is the inverted Q output.
It outputs an output voltage with a 76KHz pulse waveform as shown in Figure d. The frequency divider 7 divides the frequency (76KHz) of the output voltage of the frequency divider 6 into 1/2 and outputs an output voltage with a pulse waveform of 38KHz as shown in Figure 2e, and Q
38K shown in Figure 2 f with the output inverted as the output.
Outputs a Hz pulse waveform output voltage. In addition, frequency divider 2 adjusts the frequency (38KHz) of the output voltage of frequency divider 7.
Divide the frequency by 1/2 and output the 19KHz output voltage to the phase comparator 1. In this case, the phase of the output voltage of the frequency divider 2 lags the phase of the input pilot signal input to the phase comparator 1 by 90 degrees.

Therefore, the output voltage of the waveform shaping circuit 9, the frequency divider 6
The pulse output voltage shown in FIG. 2g is output as a switching output voltage to the output terminal of the NOR gate 10 which receives the output voltage of the frequency divider 7 and the output voltage of the frequency divider 7 as inputs. In addition, the output voltage of the waveform shaping circuit 9,
A pulse voltage shown in FIG. 2h is outputted as a switching output voltage to the output terminal of the NOR gate 11 which receives the output voltage of the frequency divider 6 and the Q output voltage of the frequency divider 7 as inputs. In this case, the frequency of the switching pulse obtained from the NOR gates 10 and 11 is 38 KHz, and the fall of the switching pulse is regulated by the rise position of the output voltage of the frequency divider 6. Also Noah Gate 1
The rising edge of the switching pulse obtained from 0 and 11, that is, the pulse width of the switching pulse, is determined by the slice level L of the waveform shaping circuit 9, and as the slice level L is increased, the pulse width of the switching pulse is narrowed. be able to. Also, Figure 2 g obtained from Noah Gate 10
The switching pulse shown in FIG. 2 and the switching pulse shown in FIG. 2 h obtained from the NOR gate 11 are as follows.
It has a phase difference of 180 degrees.

Next, the phase relationship between the composite signal and the subcarrier will be explained with reference to FIG. 3, focusing on the falling edge of the switching pulse obtained from the NOR gates 10 and 11.

Figure 3 shows the waveforms of the subcarrier, pilot signal, output voltages of frequency dividers 6 and 7, and output voltages of NOR gates 10 and 11 when the PLL circuit is in a locked state, and shows the phase relationship on the time axis. is always maintained in the relationship shown in FIG.

That is, although FIG. 3a shows the waveform of the 38 KHz subcarrier, it is suppressed in the actual composite signal. FIG. 3b shows the pilot signal. Third
Figure c shows the 19KHz output voltage waveform output from the frequency divider 2. FIGS. 3d and 3e show the Q output voltage waveform and output voltage waveform of the frequency divider 7, and the frequency thereof is 38 KHz. FIG. 3f shows the output voltage waveform of the frequency divider 6, and its frequency is 76 KHz.
3g shows the waveform of the switching pulse output from the NOR gate 10, and FIG. 3h shows the waveform of the switching pulse output from the NOR gate 11. The pilot signal input to the phase comparator 1 shown in FIG. 3b and the output voltage shown in FIG. The error component in the lock state is zero in terms of DC component. Furthermore, the Q output voltage and the output voltage of the frequency divider 7 are pulse waveforms of 38KHz, and as shown in Fig. 3 d and e, they are in phase (or in opposite phase) with the subcarrier shown in Fig. 3 a. ,
The rise of the output voltage of the frequency divider 6 coincides with either the positive peak point or the negative peak point of the subcarrier, as shown in FIG. 3f. Therefore, since the trailing edge of the switching pulse shown in FIGS. 3g and 3h obtained from the NOR gates 10 and 11 is regulated by the rise of the output voltage of the frequency divider 6 shown in FIG. 3f, This exactly coincides with the peak point of the subcarrier shown in FIG. 3a.

Therefore, the composite signal shown in FIG. 4a is used to drive the switching elements with the switching pulse obtained from the NOR gate 10 shown in FIG. 4b and the switching pulse obtained from the NOR gate 11 shown in FIG. 4c, respectively. When the composite signal is separated into the left channel output and right channel output, the trailing edge of the switching pulse shown in Figure 4b coincides with the positive peak point of the subcarrier, and the switching pulse shown in Figure 4c coincides with the positive peak point of the subcarrier. Since the trailing edge of the switching pulse coincides with the negative peak point of the subcarrier, the left channel audio component and the right channel audio component can be separated and demodulated. This is the envelope of the left channel audio modulation signal shown in waveform A in Figure 4a in the time-division composite signal,
As is clear from the envelope of the right channel audio modulation signal shown in waveform B in FIG. 4a and the subcarrier waveform shown in waveform C in FIG. 4a, the left channel audio modulation signal is included only at the positive peak point of the subcarrier. This is because the right channel audio modulation signal is included only at the negative peak point of the subcarrier.

In addition, in the above embodiment, the case where the trailing edge of the switching pulse coincides with the positive peak point and the negative peak point of the subcarrier was explained as an example. The peak point of
The switching pulse may be generated to coincide with the negative peak point, or the switching pulse may be generated so as to include the peak point of the subcarrier.

As explained above, according to the present invention, the width of the switching pulse is obtained by waveform shaping the output signal of the voltage controlled oscillator, rather than using the conventional method of using a time constant circuit. It is stable as there are no elements that affect it.

Furthermore, the switching pulse is obtained by extracting and synthesizing the signal waveforms existing in the PLL circuit, so it is stable.

Furthermore, the circuit configuration is simple and it is easy to integrate the circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention.
Fig. 2 is an output voltage waveform diagram of a voltage controlled oscillator, waveform shaping circuit, frequency divider, and NOR gate to explain the operation of an embodiment of the present invention, and Fig. 3 is an illustration of the output voltage waveforms of the voltage controlled oscillator, waveform shaping circuit, frequency divider, and NOR gate to explain the operation of an embodiment of the invention. FIG. 4 is a waveform diagram of a composite signal, a subcarrier, and a switching signal to explain the operation of an embodiment of the present invention. 1... Phase comparator, 2, 6 and 7... Frequency divider, 3... Low pass filter, 4... DC amplifier, 5... Voltage controlled oscillator, 9... Waveform shaping circuit, 10 and 11... NOR gate .

Claims (1)

[Scope of utility model registration request] This is a switching pulse generation circuit that generates switching pulses for a switching type stereo demodulation circuit, and includes a voltage-controlled oscillator that oscillates at 152KHz when locked, and a voltage-controlled oscillator that changes the oscillation frequency of the voltage-controlled oscillator.
A first frequency divider that divides the frequency of the output voltage of the first frequency divider to 38KHz, and a second frequency divider that divides the frequency of the output voltage of the second frequency divider to 38KHz. 19K
a third frequency divider that divides the frequency into Hz; a PLL circuit configured to control the output voltage of the voltage controlled oscillator, a waveform conversion circuit that slices the output voltage of the voltage controlled oscillator at a predetermined level and converts it into a pulse waveform voltage, and the output voltage of the waveform conversion circuit and the first frequency division. output voltage of the device and the second
A logical operation is performed on the output voltage of the frequency divider to output a first switching pulse, and the output voltage of the waveform conversion circuit, the output voltage of the first frequency divider, and the output of the second frequency divider are 1. A switching pulse generation circuit comprising: a waveform synthesizing means for performing a logical operation on an output voltage having a phase opposite to the voltage and outputting a second switching pulse.