JPH0432821Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] This invention relates to an improvement in reducing the power consumption of a phase-locked circuit.

[Prior art and its problems]

Synthesizers using phase synchronization circuits are currently being used as radio equipment becomes multi-channel.
FIG. 2 is a block diagram thereof, and FIG. 3 shows waveforms of various parts during phase synchronization of the loop filter with respect to the reference voltage Es. In FIG. 2, the signal of the reference signal generator 1 is frequency-divided by a frequency divider 2 to generate a pulse output a. On the other hand, the output of the voltage controlled oscillator 5 is frequency-divided by a frequency divider 6 to generate a pulse output b. Pulses a and b are phase-compared by a phase comparator 3 to generate an error signal c, which is integrated by a loop filter 4 and applied to a voltage-controlled oscillator 5. Due to the negative feedback effect of the phase-locked circuit, the average of the phase comparator is With a phase difference where the voltage is equal to the reference voltage Es of the loop filter, the output frequency of the voltage controlled oscillator is locked to a predetermined value.

Figure 3 shows the reference voltage Es of the loop filter with respect to the output reference level of the phase comparator during phase synchronization (the output voltage when the output side C-MOS FETs of the phase comparator are turned off at the same time, which is approximately equal to Vcc/2). This shows the output waveform of the phase comparator when . Figure 3 (1) shows when Es = Vs, and in order for both average voltages to be equal, the phase difference between the pulse waveforms of a and b is approximately 0, and the phase comparator output corresponds to the leakage current of the circuit. Only a narrow pulse giving the DC change appears on the power supply side and 0V side with Es as a reference. In the case of EsVs, in order for the average value of the phase detector output to be equal to Es, the third
As shown in FIGS. (2) and (3), a phase difference occurs between the pulses a and b, and the loop is balanced, so that the output waveform of the phase comparator generates a pulse waveform with Vs as a reference. At this time, the C-MOS FET on the output side of the phase comparator always has a period of being ON, which causes a period of current consumption compared to case 3 (1), which is an undesirable phenomenon in terms of reducing power consumption. be. In order to reduce power consumption, the reference voltage Es of the loop filter can be adjusted to be equal to Vs, but due to variations in the elements, VS may not necessarily be Vcc/2, and may vary depending on temperature, etc. In conventional circuits, it was impossible to make Es=Vs under all conditions.

〔the purpose〕

In order to eliminate the above drawbacks, the present invention uses a sampling and hold circuit following the phase comparator to accurately extract the Vs signal level of the phase comparator output.
This is used as a reference signal for the loop filter.

〔Example〕

Figure 1 is a block diagram of an embodiment of the present invention;
The figure shows the process of extracting the Vs signal level from an asynchronous state to a synchronous state in this circuit, and the operation of the present invention will be explained according to the figure. Figure 4
In states (1) and (2), the voltage controlled oscillator is asynchronous and the phase lags or leads the reference signal a, and (3)
In state (4), the phase matches the reference signal a, resulting in a synchronized state. The phase comparator output signal c is sent to the delay circuit 7
The waveform is delayed by , resulting in the waveform shown in FIG. 4d. This d
The waveform is shaped by a window comparator 8 having a reference level slightly higher or lower than Vs to obtain pulse waveforms e and f. this signal
The g waveform is output through the OR circuit, and the pulse generating circuit 9 generates the sampling pulse h. As shown in Fig. 4, this sampling pulse is delayed by the time constant of the delay circuit 7 from the phase difference output pulse regardless of whether the circuit is synchronous or asynchronous.The c signal is used as the input, and the h pulse is used as the sampling pulse input. The sample-and-hold circuit 10 can accurately extract the Vs signal shown by the black dot in waveform c in FIG. Therefore, by inputting this sample value (that is, Vs) to the reference signal of the loop filter, the phase of the voltage controlled oscillator matches the reference signal as described above, and therefore the pulse width generated at the phase comparator output becomes very large. It can be made thin and the current consumed by the phase comparator can be minimized. In the above embodiment, the operation of the circuit has been described with respect to an example in which the reference level is extracted from the output signal of the phase comparator, but it is clear that the same operation can be performed using other circuits.

〔effect〕

As described above, according to the present invention, it is possible to minimize the power consumed by the phase comparator of a phase-locked circuit, and it is possible to minimize the power consumed by the phase comparator of a phase-locked circuit.
It is especially effective when used in equipment that requires low power consumption.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a phase locked circuit according to an embodiment of the present invention, Fig. 2 is a conventional block diagram of the same as above, and Fig. 3 is a block diagram of a phase synchronized circuit according to an embodiment of the present invention.
This figure is an explanatory diagram of the operation of FIG. 2, and FIG. 4 is an explanatory diagram of the operation of FIG. 1. 1... Reference signal generator, 2, 6... Frequency divider, 3
...Phase comparator, 4...Loop filter, 5...
Voltage controlled oscillator, 7...Delay circuit, 8...Window comparator, 9...Pulse generation circuit, 10...
...Sampling hold circuit.

Claims (1)

[Scope of utility model registration request] a reference signal generator, a first frequency divider that divides the frequency of the reference signal generated by the reference signal generator, a voltage controlled oscillator, a second frequency divider that divides the output of the voltage controlled oscillator; The phases of the frequency divider output and the second frequency divider output are compared, and approximately 1/2 of the power supply voltage is set as a reference level for a time proportional to the phase difference, and the power supply voltage or 0V value is adjusted to correspond to the phase lag or lead. In a phase synchronized circuit having a phase comparator that outputs a pulse, and a loop filter consisting of an operational amplifier that integrates the output of the phase comparator and whose output is input to a voltage controlled oscillator, the output of the phase comparator is delayed. A delay circuit, a window comparator that shapes the output waveform of the delay circuit at a reference level that is slightly higher or lower than the reference level of the phase comparator, and generates a sampling pulse at the falling point of the output pulse of the window comparator. A phase comparator reference level extracting means is provided, which includes a pulse generating circuit that holds the output of the phase comparator using the sampling pulse, and a sample hold circuit that holds the output of the phase comparator using the sampling pulse, and the obtained reference level is used as the reference voltage of the operational amplifier. A phase-locked circuit featuring: