JPS6243607B2 - - Google Patents

Description

[Detailed Description of the Invention] In a system that records a POM signal obtained by converting a music signal into a digital signal on a magnetic tape or video disk and plays it back, the playback signal may be distorted due to the presence of scratches or dust on the recording medium used. Signal dropout occurs during Signal errors caused by signal loss include random errors and burst errors, and various correction methods have been announced for each of the above errors, but in a POM signal recording and reproducing system using a VTR, random errors cannot be corrected. A method is used to correct errors and signals using adjacent code correction, and a method is used to randomize errors by interleaving operations for burst errors (Japan Electronics Industries Association, June 1979). Established technical file STC-007 "Consumer PCM encoder/decoder").

Fig. 1 is a block diagram of a conventional example of a PCM signal recording and reproducing system using a VTR. In Fig. 1, 1a and 1b are input terminals, and analog signals supplied to the input terminals 1a and 1b are , A.D.
The converter 2 converts it into a PCM signal. (A.D.
The converter 2 also includes a low-pass filter, a sample-and-hold circuit, a time division circuit, etc.).

The digital signal output from the AD converter 2 described above is given to the signal switching circuit 14 and the error correction word generation circuit 15.
The error correction word created by is also applied to the switching circuit 14. The switching circuit 14 performs a predetermined switching operation and supplies the six sampled signal words and two error correction words arranged as required on the time axis to the memory circuit 3, Circuit 3 stores the information given to it.

Further, the memory circuit 3 performs a predetermined interleaving operation on the information stored therein, and the information read from the memory circuit is provided to the mixer 6 and the error detection word generation circuit 5. The above mixer 6 receives the output signal of the error detection word generation circuit 15 and a specific standard signal generated by the composite synchronization signal generator.
Since a composite sync signal that conforms to the TV scanning standard is also provided, it is output from mixer 6 and output to VTR 7.
The signal given to is a PCM signal in a signal format that conforms to the TV signal of the standard TV system.

Figure 2 shows PCM recorded and played back by a VTR.
It shows the data arrangement within one horizontal synchronization period of the signal, and in this figure, A and B are two of the music signal.
The sampled signal words according to the channel information are shown, and in FIG. 2, six sampled signal words A, B,
A... and the six sampled signal words A, B, A
A block signal is shown in which error correction words P and Q generated from . . . and an error detection word CRC are arranged.

PCM signal output from VTR7 (standard method)
The PCM signal (which has a signal format compliant with the TV signal and in which a block signal exists within one horizontal synchronization period as shown in the second figure) is converted into digital data and a TV composite synchronization signal by the comparator 8. Separated. The digital data output from the comparator 8 is
Delay circuit 9 (1H digital delay circuit 9) for one horizontal synchronization period (1H) via serial-parallel conversion circuit 16
is given and latched for a period of 1H, and then the next 1
The signal is input to the memory circuit 10 during the horizontal synchronization period.

Further, the digital data output from the comparator 8 is also given to the error detection circuit 17, and the error detection circuit 17 detects the presence or absence of an error in the block signal within each 1H interval using the error detection word CRC. Then, the detection result is input to the memory circuit 10.

The interleaved digital data provided from the 1H delay circuit 9 to the memory circuit 10 is deinterleaved by the operation of the memory circuit 10, and is also deinterleaved by the operation of the memory circuit 10 and the correction circuit 11.
The erroneous data due to the operation of
Signals of two channels A and B are sent from b (the DA converter 12 includes a time division circuit, a low-pass filter, etc.).

Further, the horizontal synchronizing signal outputted from the comparator 8 described above is given as a timing signal for the start of operation of the control signal generation circuit 18, and various control signals generated by the control signal generation circuit 18 are converted into serial and parallel signals. Circuit 16, 1H delay circuit 9, error detection circuit 1
7, supplied to the memory circuit 10, correction circuit 11, DA converter 12, etc.

FIG. 3 is a time chart for explaining the problems in the conventional system shown in FIG. 1, and _FIG . 3b shows the control signal generating circuit 1 based on the horizontal synchronizing signal _Ph .
The waveform diagram of the correction operation start signal Pa generated in step 8 and FIG.

Now, in the conventional system shown in FIG. 1, when the horizontal synchronizing signal P _h shown in FIG. is cleared and starts counting, and the decoder to which the counter output is applied generates various timing signals (control signals) at predetermined time positions to control the operations of each component. is being done.

Then, the memory circuit 10 writes new 8 words of digital data output from the 1H delay circuit 9 within one horizontal synchronization period (1H) {periods T ₂ and T ₄ in FIG. }, reading of digital data sent to the DA converter 12 at fixed time intervals {T ₁ , T ₃ , T ₆ , T ₈ , T ₁₁ , in FIG. 3c,
T ₁₅ period}, reading out 8 words of deinterlaced digital data {in Figure 3 c)
T ₅ , T ₇ , T ₉ periods}, operation for error correction by adjacent code correction {T ₁₀ , T ₁₂ periods in Figure 3c}, writing of corrected digital data {3rd period)
Various operations must be performed such as {period T ₁₃ in Figure 3 c}, {period T ₁₄ in Figure 3 c,
_T16 indicates a margin time}, but in order to enable the memory circuit 10 to stably and reliably perform the above-mentioned various operations within a 1H period, the above-mentioned series of various operations have an allowable time. A sufficiently long time is allocated within the range, and the margin time is small.

Therefore, if the horizontal synchronization signal appears at a time position much shorter than the regular 1H time interval for some reason, it will be generated from the control signal generation circuit 18 at the same timing as the horizontal synchronization signal _Ph . By the correction operation start signal Pa {Figure 3b},
At that time, the correction operation in progress is interrupted,
Since the correction operation for the new horizontal synchronization section is started, noise may occur in the reproduced sound when the digital data whose errors are not corrected due to the interruption of the correction operation is converted to DA. Sometimes things happen.

The above problem does not occur if the synchronization of the horizontal synchronizing signal is always in a normal state, but due to dropout or skew, the horizontal synchronizing signal appears, for example, at P _h ' at the dotted line position in Figure 3. When this happens, a correction operation start signal is generated at position Pa' in Figure 3, interrupting the error correction operation in progress at that time, which causes a big problem especially when recording and reproducing using a VTR. It will become.

The above point will be specifically explained below with reference to FIGS. 3 and 6. Fig. 6a shows one horizontal synchronization period that starts at time t1 and should originally end at time t3, but is shortened due to causes such as skew, and the next horizontal synchronization period Ph appears at time t1. This shows the state of the signal when the signal Ph' appears at time t2, and in this case, of course, data after time t2 in the interlaced digital data is deleted. The position of the horizontal synchronizing signal Ph' appearing at time t2 in FIG. 6a is the same as the horizontal synchronizing signal indicated by the dotted line in FIG. 3a.
The position is the same as that of Ph′.

The digital data in the state shown in FIG. 3a when there is no skew is generated by the correction operation start signal Pa shown in FIG. 3b, which is generated by the control signal generation circuit 18 based on the synchronization signal Ph. Therefore, the correction operation for the digital data in the correction circuit 11 is started, and T10 and T10 in FIG.
Calculation for error correction by adjacent code correction is performed during the period T12, and the corrected digital data
Xw and Yw are written into the memory 10 during the period T13 in FIG. 6a in the correction circuit 11 by the correction operation start signal Pa in FIG. 6b generated by the control signal generation circuit 18.
6 is generated by the control signal generation circuit 18 based on the next horizontal synchronization signal Ph' that appears at time t2 due to skew after the correction operation for the digital data in the state shown in the figure is started. The correction circuit 11 is activated by the correction operation start signal Pa′ shown in FIG.
The correction operation that was continuing at that time is interrupted, and
In order to start the correction operation by the new correction operation start signal Pa' generated at time t2, the correction circuit 11 performs adjacent code correction during the period T12 shown in parentheses in FIG. 6c. The calculation for error correction by , and the writing operation of the corrected digital data Xw, Yw to the memory 10 during the period T13 shown in parentheses in Figure 6c will not be performed. As a result, as mentioned above, digital data whose errors have not been corrected is subjected to DA conversion, causing noise in the reproduced sound. In addition, the 6th
The displays such as A, B, etc. shown at the bottom of the margin in Figure c are written to the memory in a state where they are located in the corresponding column in the diagram due to the occurrence of the above-mentioned skew. The digital data for one horizontal synchronization period is shown.

The present invention has been made to solve the above-mentioned conventional problems, and the specific contents of the data correction circuit of the present invention will be explained in detail below with reference to the accompanying drawings. FIG. 4 is a block diagram of a PCM signal recording and reproducing system including the data correction circuit of the present invention. In this FIG. are given the same drawing symbols as those used in FIG. 1.

In FIG. 4, 1a and 1b are input terminals for analog signals of two channels A and B, 2 is an AD converter, 3 is a memory circuit, 4 is a composite synchronous signal generator,
5 is an error detection word generation circuit, 6 is a mixer, and 7 is an error detection word generation circuit.
VTR, 8 is a comparator, 9 is a 1H delay circuit, 10 is a memory circuit, 11 is a correction circuit, 12 is a DA converter,
13a and 13b are analog signal output terminals, 14
1 is a switching circuit, 15 is an error correction word generation circuit, 1
6 is a serial-to-parallel conversion circuit, and 17 is an error detection circuit, and these parts are the same as those of the conventional example shown in Figure 1 described above.
It is similar to the POM recording/playback system.

In FIG. 4, 19 is a first control signal generation circuit, 20 is a delay circuit (digital delay circuit), and 21
is a second control signal generation circuit, in which the horizontal synchronization signal P _h separated by the comparator 8 is supplied to the first control signal generation circuit 19 and the delay circuit; The horizontal synchronizing signal P _hd delayed by the delay circuit 20 is applied to the circuit 21 .

The first control signal generating circuit 19 to which the horizontal synchronizing signal P _h {Fig. 5a} is supplied includes, for example, a counter and a decoder, and each time the horizontal synchronizing signal P _h is supplied, Start counting operation,
Various control signals having required timings are obtained from the decoder, and interlaced data write signals and other signals are supplied to the memory circuit 10, and the digital 1H delay circuit 9, the serial/parallel converter circuit 16, Predetermined control signals are given to the error detection circuit 17, DA converter 12, etc., respectively.

Also, the delayed horizontal synchronization signal P _hd {Fig. 5b
} is supplied to the second control signal generation circuit 21
is composed of, for example, a counter and a decoder, and based on the delayed horizontal synchronizing signal P _hd , it outputs a correction operation start signal Pa (Fig. 5c) and other control signals (for example, 10 and a signal for writing corrected data into the memory circuit 10.

As described above, in the data correction circuit of the present invention, the correction operation start signal Pa is generated based on the delayed horizontal synchronization signal P _hd obtained by delaying the horizontal synchronization signal P _h by the delay circuit 20. Since the correction operation is started, as shown in Fig. 5 d, the margin time increases significantly compared to the case shown in Fig. 3 c, which was already mentioned, and also reduces the risk of skew. Therefore, even if the horizontal synchronizing signal appears at a position shorter than the 1H period, it is possible to prevent the correction operation from being interrupted.

In FIG. 5, P _h ' is a horizontal synchronizing signal caused by skew, etc., and P _h ' _d is a horizontal synchronizing signal P _h '
is the delayed signal.

The above point will be specifically explained below with reference to FIGS. 5 and 7. FIG. 7a shows one horizontal synchronization period that starts at time t1 and should originally end at time t3, but is shortened due to causes such as skew, and the next horizontal synchronization period of the horizontal synchronization signal Ph that appears at time t1 This shows the state of the signal when the signal Ph' appears at time t2, and in this case, of course, data after time t2 in the interlaced digital data is deleted. The position of the horizontal synchronizing signal Ph' appearing at time t2 in FIG. 7a is the same as the horizontal synchronizing signal indicated by the dotted line in FIG. 5a.
The position is the same as that of Ph′.

When there is no skew, the digital data in the state shown in FIG. 5a is delayed as shown in FIG. Horizontal sync signal
The correction operation for the digital data in the correction circuit 11 is started by the correction operation start signal Pa shown in FIG. 5c generated by the second control signal generation circuit 21 based on the T1
Calculation for error correction by adjacent code correction is performed during the period T12, and the corrected digital data Xw and Yw are written to the memory 10 during the period T13 in FIG. Error correction is performed by

Further, a horizontal synchronization signal Phd generated by the second control signal generation circuit 21 is generated based on the delayed horizontal synchronization signal Phd as shown in FIG. After the correction operation start signal Pa in FIG. 7c starts the correction operation for the digital data in the state shown in FIG. When the horizontal synchronizing signal Ph' appears, the horizontal synchronizing signal Ph' is delayed by the delay circuit 20 to become the delayed horizontal synchronizing signal Phd' as shown in FIG. 7b, and the delayed horizontal synchronizing signal Ph' is The correction operation start signal Pa' at time t4 in FIG. 7c is generated by the second control signal generation circuit 21 based on the signal Phd'. The correction circuit 11 starts the correction operation at time t4 by the correction operation start signal Pa' shown in FIG. Previously, as shown in Figure 7d, T1
Since the operation for error correction by adjacent code correction in the period T13 and the writing operation of the corrected digital data Xw, Yw to the memory 10 in the period T13 have already been completed, the data correction circuit of the present invention In this case, even if there is a skew, the correction will be performed by a good correction operation.

Therefore, in the data correction circuit of the present invention, the third
Unlike the conventional data correction circuit described with reference to FIG. It is. In addition, the indications such as A, B, etc. shown in the lower part of the margin in Figure 7d are in a state where they are located in the corresponding part of the diagram due to the occurrence of the above-mentioned skew. It shows digital data for one horizontal synchronization period written into the memory. If skew occurs as described above, the input digital data written to the memory will no longer be normal, but there is no problem because errors in the input data will be corrected by the correction operation. However, the third
In the case of the conventional data correction circuit explained with reference to FIG. 6 and FIG. The above-mentioned problems occur because data that is erroneously determined as uncorrectable is output.

In the embodiment described with reference to FIG. 4, the delay circuit 2 is used to delay the horizontal synchronization signal _Ph .
0 is used, but in implementation, the decoder output in the first control signal generation circuit 19 is used instead of the delayed horizontal synchronization signal P _hd , and it is applied to the second control signal generation circuit 21 (the The connection mode shown by the dotted line in FIG. 4 may be used, and the delay circuit 20 may be omitted. The amount of delay to be given to the horizontal synchronizing signal is determined by the fact that the start of the correction operation is when the correction data is transferred from the memory circuit 10 {data in FIG.
W ₁ , W ₂ . . . , considering that the PCM signal starts at the 31st clock of 2.6MHz from the falling edge of the horizontal synchronization signal _Ph ,
Approximately 30 clocks may be selected with a 2.6MHz clock.

As is clear from the above explanation, when the data correction circuit of the present invention is adopted, even when the horizontal synchronization period is shortened due to skew, the correction operation is performed well and error correction is performed. There is no noise caused by malfunctions as mentioned in the conventional example, and even in normal operation mode, data processing time that is essential to the system and unrelated to calculations is reduced.
Since all of these can be added to the calculation time margin, it is possible to use slow logic elements, and furthermore, various advantages such as ease of integration into integrated circuits can be obtained.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a PCM signal recording and reproducing system using a VTR, Figure 2 is a data arrangement diagram within a horizontal synchronization section, Figures 3 and 6 are time charts of conventional correction operations, and Figure 4 is a diagram of a PCM signal recording and reproducing system using a VTR. The block diagram of one embodiment of the present invention, FIGS. 5 and 7, are time charts showing the correction operation of the present invention. 9...1H delay circuit, 10...memory circuit, 11...
Correction circuit, 19...first control signal generation circuit, 21
...Second control signal generation circuit.

Claims (1)

[Claims] 1 A digital signal sequence arranged in time series is divided into n pieces, and m error correction signals generated from the divided n data signals are added to the digital signal sequence, and this is the first data block. New n digital signals created discretely on the time axis and m
A new second data block is constructed by combining the error correction signals of
data blocks are arranged within a certain synchronization signal section and recorded or transmitted, and during playback, the second data block group is sequentially converted into the first data block, and the data in the second data block is Errors in the data signal that occur during recording or transmission are detected in the signal using the error detection code, and the error correction signal in the first data block is used to restore the original digital signal. The apparatus includes a correction calculation circuit that executes an operation in synchronization with a synchronization signal that defines the synchronization signal section, which includes a synchronization signal detection means and a data signal of a second data block in synchronization with the detected synchronization signal. The contents of the first memory circuit are read out within a time period shorter than the synchronization signal period in synchronization with the synchronization signal, and this data signal is converted into a time-series signal again. and a delay of a predetermined time duration shorter than the time duration from the time of the detected synchronization signal to the time of completion of reading the contents from the first memory circuit. A data correction circuit comprising means for delaying a synchronization signal by a delay circuit having a time and outputting a correction operation start signal.