JPS6243212A - Semiconductor electronic switch - Google Patents

Abstract

PURPOSE:To decrease the noises produced when a switch is turned on and off by connecting the source and the drain in parallel with each other between a P channel FET and an N channel FET together with the correcting P and N channel FET connected to one or both of two terminals and securing the balance with the gate-terminal capacity and the gate capacity. CONSTITUTION:The substrates of P channel FETs 51, 53 and 54 are fixed at a high voltage power supply VDD. While the substrates of N channel FETs 52, 55 and 56 are fixed at a low voltage power supply GND. The widths of the correcting P channel FETs 53 and 54 and correcting N channel FETs 55 and 56 are set at about 1/2 width of the switching P and N channel FETs 51 and 52 respectively. Therefore the sizes and capacities of the FETs 53, 54 as well as 55 and 56 are varied in proportion to the sizes of the FETs 51 and 52. Thus the parasitic capacity and the channel capacities of both FETs 51 and 52 are always eliminated. This prevents the impulsive noises produced to an output voltage waveform when an electronic switch is turned on and off.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to semiconductor electronic switches, particularly CMO8 (
Complementary MO8) PI! This invention relates to an electronic switch using an iT (field effect transistor).

[Technical background of the invention and its problems]

Figure 3 shows the configuration of an electronic switch using a slave ICMO8) transistor. In the figure, 11 is a P-channel type PET, and 12 is an N
? Janel type FET, 73°14 is p channel 'F'BT
The parasitic capacitance %Is, 16 created between the f gate of II and the signal input/output terminal is the parasitic capacitance created between the gate of the N-channel FETzz and the signal input/output terminal. The 0MO8 electronic switch shown in FIG. 3 is a device having a structure in which a parallel circuit of a P-channel FET 11 and an N-channel FET 12 is provided between a signal input terminal 11 and a signal output terminal 18.

In this device, in order to keep the on-resistance of the electronic switch itself approximately constant regardless of the signal voltage, P? Yanel FETMJ
Considering the carrier mobility of the Nf channel PET 12, N? The transistor channel width of Yanel PET12 is P
It is often made smaller than the transistor channel width of channel FBTZJ. Therefore, the parasitic capacitance Is,16 between r-) of Nf channel FtT12 and the signal input/output terminal is p
This is smaller than the parasitic capacitance 13.14 between the getter signal input and output terminals of the f-Yanel FBT7J.

The control signals given to the 0MO8 electronic switch are shown in FIG. 4, where 21 is the r-) signal of the Pf channel ETII, and 22 is the P? This is the output voltage waveform of the signal output terminal 18 when only the r−) signal of + channel FET J1 is applied, and 2
3 is Nf-wne, 1m/FBT12f) gate signal, 2
4 is the output voltage waveform of the signal output terminal 18 when the r-to signal of the Nf-Yanel FET Jz is applied. 25 is the output voltage waveform of the signal output terminal 18 when the signals 21 and 23 are simultaneously applied to each gate K, and the sum of the output waveforms 22 and 24 is output. The status of the 0MO8 electronic switch is
26 sections are on.

Section 21 is off.

When the electronic switch is turned on and off in output waveform 25, noculus-like noise is generated in the waveform, which is caused by P? This is thought to be because the parasitic capacitance of Janel FET1z is also large (as compared to the parasitic capacitance of N-channel FBTJj), so in order to reduce noise generation, parasitic capacitance is added to the signal input terminal and signal output terminal as shown in Figure 5. The capacitance jj that cancels out the difference is added to 341, and in FIG. -G, 44 is P well, 45 is N type substrate%4
Reference numeral 6 is an insulating film, and here the Nf channel PET source and drain regions 41 and 42t- are widened, and the overlapped portion with p-) 43 is enlarged to form a source region connected to the gate 43 and the signal input/output terminal. 4. A method was used in which a capacitor 11 was added between the drain region 42 to cancel out the difference in parasitic capacitance.

As mentioned above, as a method for reducing pulse-like noise that occurs when switching on and off in electronic switches, conventionally, the fifth
As shown in FIG. However, when the switch is turned on and off, and when the voltage at the signal input terminal changes, Pf-Yanel F'B'r.

N? It has been found that this method is insufficient as a noise reduction method if the correction of the channel capacitance of the gate of the Yarnel PET is not taken into consideration.

[Purpose of the invention]

The present invention aims to reduce noise when switching on and off of CMO8 [child switch].
The cause of this noise is the parasitic capacitance between r-) of the P-channel PET and the signal input and output terminals and %N? N channel F
Difference in parasitic capacitance between ET gate signal input and output terminal,
By focusing on the difference in channel capacitance between P-channel PET and Nf-channel PET, noise is reduced by balancing parasitic capacitance and channel capacitance.

[Summary of the invention]

The present invention can be applied to the source, drain and N? of a P-channel PET.
- Connect the source and drain of Yanel FIT in parallel,
Use one end as a signal input terminal.

The other end is used as a signal output terminal, and the source and drain are connected to one or both of these terminals for correction. ET, N-channel FET is connected, and its FB
The e-) signal of T is the r- signal of P-channel PET in the switch section.
) Is the signal N for correction? Yarnel FBT's r-) signal and
N in the switch part? Yanel FET? -) signal is a correction P″f medium FETC)?”-) signal, thereby P5+-Yanel FBIT,
This balances the capacitance between the terminals of both f-gates of the Nf channel PET and the gate capacitance, thereby achieving noise reduction when the switch is turned on and off.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, signal input terminal 58. The source and drain of the switch P-channel FBT 51 are connected between the signal output terminals 59, and the switch N-channel FE is connected in parallel to this PET.
TgJ'i connected, FBTSI (D'r”-)K signal 1
supply.

A gate K signal φ of FETjj is supplied. The gate signal 7 is obtained by inverting the gate signal φ with an inverter 57. Correction P channel pE'f53.
54 have their sources and drains connected, and are FETj
FET j4 is connected to the signal input terminal 58, FET j4 is connected to the signal output terminal za9, and the date signal φ is applied to FBTSI,54. N channels for correction]; 'ET55 and 56 have their sources and drains connected, FBTSI is connected to the signal input terminal 58, and FF and T56 are connected to the signal output terminal 59.

The r-) signal 7 is applied to FETs 55 and 56. The substrates of P-channel FETs 51, 53, and 54 are connected to a high voltage power supply (V
D) ) fixed to Nf channels P3T52,55.
A low voltage power supply (QND) K is fixed to the board 56. Another correction P? The channel width of the Yarnel FBTs 53 and 54 is set to approximately A of that of the switch P-channel FBT 51, and the channel width of the correction N-channel FETs 5j and sr is set to N? for the switch. It is set to approximately S of Yarnel FBT12. i
Switch FET51, 52 and correction FBTss~5
In No. 6, the on/off relationship is reversed.

By configuring as above, P channel FET5
The parasitic capacitance created between the J r-) and signal input/output terminals is charged to the FET 53 containing the inverse r-) signal.
．． 54 and is canceled by being accumulated in the parasitic capacitance of I! Differences in channel capacity due to different sizes of FBTSI, 52 are also canceled. Similarly, the charge on the parasitic capacitance generated between the r-) signal input and output terminals of the N-channel FBT 5J is canceled by accumulation of the parasitic window tK of the FBTSI, 51, which contains the reverse gate signal, and , 52 are also canceled. In other words, FBT is proportional to the size of FETjj and 52.
The magnitude of SI, 54 and 55.58 and the channel capacity of 7 also change constantly in FBTSI.

This is a method of canceling out the parasitic capacitance and f-Jannel capacitance at 52, and can prevent noise-like noise from occurring in the output voltage waveform when the electronic switch is turned on and off.

FIG. 2 is a characteristic diagram of the above-mentioned electronic switch, where %62 is an N-channel 1PERsztD)y''-) signal, and 63 is a gate signal of the P-channel FET 51.

61 is an output voltage waveform at a conventional signal output terminal. C
The state of the MO8 electronic switch is that 64 is an on period and 65 is an off period.In the electronic switch of the present invention, a noise-free output voltage waveform as shown in 66 can be obtained due to the cancellation effect of the parasitic capacitance and channel capacitance. It will be done.

Note that the present invention is not limited to the embodiment, and can be applied in various ways. 8For example, in the embodiment, a correction FET is provided at both the signal input terminal and the signal output terminal, but even one of the correction PETs is Because it has a charge canceling effect,
Only one of the correction FETs 53 and 54 and one of the FETjj and 5if may be provided.

〔Effect of the invention〕

As explained above, the electronic switch of the present invention is different from the conventional 0M
Compared to the O8 electronic switch, this switch has the advantage of being able to prevent noise at the time of switching by making noise in the form of a noise very small when the switch is switched on and off.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a signal waveform diagram of the same circuit, Fig. 3 is a circuit diagram showing a conventional electronic switch, Fig. 4 is a signal waveform diagram of the same circuit, and Fig. 4 is a signal waveform diagram of the same circuit. FIG. 5 is a circuit diagram for explaining improvements in the conventional electronic switch, and FIG. 6 is an FET configuration diagram for explaining other improvements in the conventional electronic switch. 51...Pf channel ET for switch %52...N-channel FET for switch, 5J, 54...Pf for correction
Tonel FT! , T, 55.56... Correction N-channel FET 15g... Signal input terminal, 59... Signal output terminal. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (2)

[Claims] (1) The source and drain of a first P-channel FET (field effect transistor) are connected between the signal input terminal and the signal output terminal, and the first
A second N-channel P FET is connected to the N-channel FET, and is controlled by the same gate signal as the gate signal of the first P-channel FET.
ET, and a second P-channel FET controlled by the same gate signal as the gate signal of the first N-channel PET, and the second N-channel FET and the second P-channel FET each have a A semiconductor electronic switch characterized in that the source and drain are connected to one or both of the input terminal and the signal output terminal. (2) The substrates of the first and second P-channel FETs are fixed to a high voltage power supply, and the substrates of the first and second N-channel FETs are fixed to a high voltage power supply.
2. A semiconductor electronic switch according to claim 1, wherein the substrate is fixed to a low voltage power source.