JPS6243196B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable automatic performance device in which musical scores can be programmed, and more particularly to a programmable automatic performance device that can fast-forward the address designation of a musical score memory during musical score programming or automatic performance.

Generally, automatic musical performance devices capable of programmable musical scores can specify a predetermined address in the musical score memory, but cannot continue automatic performance. Also, a fast-forward function for specifying music score memory addresses was not added.

The present invention provides a programmable automatic performance device that fast-forwards to a predetermined address in a musical score memory during programming or automatic performance, and is capable of continuing programming or automatic performance.

The present invention will be described below with reference to drawings of embodiments.

FIG. 1 shows an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a pitch input section, which specifies a predetermined pitch and outputs pitch information and a pitch pressing signal. Reference numeral 2 denotes a pitch code conversion section, which inputs pitch information from the pitch input section 1 and converts it into a predetermined code. Reference numeral 3 denotes a tone length input section, which specifies a predetermined tone length and outputs tone length information and a tone length pressing signal.
4 is a tone length code conversion section, and the tone length input section 3
The input tone length information is converted into a predetermined code. Reference numeral 5 denotes a tone length temporary storage section, which receives the output signal (tone length coded signal) of the tone length code conversion section 4 and the tone length press signal of the tone length input section 3 and generates a tone length press signal. Each time, the tone length encoded signal is stored. 6 is a P/A switch, which distinguishes between program state P and automatic performance state A. Reference numeral 7 denotes a musical score memory, which is in a musical score data writing state when the P/A switch 6 is in the program state P, and is stored in the pitch code converting section every time a pitch pressing signal is output from the pitch input section 1. 2 output signal (pitch coded signal) and the output signal of the pitch temporary storage section 5 are stored at a predetermined address, and when the P/A switch 6 is in the automatic performance state A, the output signal is read out; Musical score data (pitch, length) written according to the specified address is read out in sequence. Reference numeral 8 denotes an address designation section for designating the address of the musical score memory 7. 9 is a pose switch,
Pause during automatic play. Reference numeral 10 denotes a fast-forward switch, which fast-forwards the address designation of the musical score memory 7. 11 is an oscillator, which determines the fast forwarding speed. 12 is an address counter, which counts up one step when a clock signal is input from the clock input CK and specifies the address of the score memory 7; Clear the address specification of memory 7 to address 0. 13 is a clear switch, and when it is closed, a low level is sent to the clear input CR of the address counter 12 to clear the address counter 12. Reference numeral 14 denotes a musical score generator, which inputs the output e (pitch data) of the musical score memory 7, forms musical tones, and outputs musical tone signals. 15 is a tempo oscillator, which determines the tempo of automatic performance. Reference numeral 16 denotes a note length counter, which receives the output (note length data) of the musical score memory 7 as input and counts the note length based on the oscillation frequency of the tempo oscillator 15. 17, 18 are inverters, 19,
20, 21 are AND gates that perform logical product; 22,
23 and 24 are OR gates that perform a logical sum.

The operation when programming a musical score in the above configuration will be explained. The P/A switch 6 is set to the program side P to put the musical score memory 7 into a writing state, and a predetermined note length is input from the note length input section 3. For example, when the tone length switch of whole note O is pressed, switches c and d move in conjunction, and tone length information is sent from switch d to the tone length temporary storage section 5 via the tone length code conversion section 4. Here, a ROM is used as the tone length code converter 4, and codes for whole notes, half notes, etc. are stored therein. Further, a tone length press signal is output from switch c. As a result, the tone length temporary storage section 5 enters a storage state and stores the pressed tone length coded information.

Next, a predetermined pitch is input from the pitch input section 1.
For example, when you press pitch switches a and b (C ₃ ), switches a and b move in conjunction, and switch b
From there, the pitch information is sent to the musical score memory 7 via the pitch code converter 2 (the pitch code converter uses a ROM to store codes for each pitch). Then, the pitch pressing signal is sent from the switch a to the score memory 7, and the pitch coded information and note length coded information are stored at a predetermined address designated by the address counter 12. Also,
A pitch press signal is also applied to the AND gate 20. Another input of the AND gate 20 is P/
Although the signal from the A switch 6 is being sent, it is on the program side P (high level), so the output of the AND gate 20 depends on the pitch press signal. Furthermore, since the signal from the P/A switch 6 is applied to the AND gate 21 via the inverter 17, the signal from the other input is blocked. Then, the pitch press signal is sent to gate 20,
22 and 23 to the clock input CK of the address counter 12. When the pitch pressing signal changes from a high level (ON) to a low level (OFF), the address counter 12 counts up by one step and advances the designated address in the musical score memory by one step. In this way, musical score data can be sequentially input to the program.

Now, suppose that the address specification for music score memory 7 is number 10.
If you want to skip to addresses 11 to 20, just press the fast forward switch 10. Here, oscillator 1
The oscillation frequency of 1 is higher than the average frequency of the output pulses of the tone length counter 16. When the fast forward switch 10 is pressed, the gate 19 is opened, and the output signal of the oscillator 11 is passed through the gates 19 and 23 to the clock input CK of the address counter 12.
sent to. Then, the address designation of the musical score memory 7 changes at a speed corresponding to the oscillation frequency of the oscillator 11. Fast forward switch 1 when it reaches the specified address
When the pressing operation of 0 is released, the gate 19 enters a blocking state, the output signal of the oscillator 11 is no longer applied to the address counter 12, and fast forwarding is stopped. Then, musical score data can be input into the program.

Next, the operation during automatic performance will be explained.
Set P/A switch 6 to automatic performance side A (low level)
to put the musical score memory 7 into a reading state. P/
By setting the A switch 6 to the automatic performance side A (low level), the gate 20 is placed in a blocking state, and the output of the gate 21 depends on the output signal of the tone length counter 16 and the signal from the pause switch 9. Assuming that a high level (OFF) is now being sent from the pause switch 9 to the gate 21, the output of the gate 21 depends only on the output signal of the note length counter 16. Then, when the clear switch 13 is changed from high level (OFF) to low level (ON) to (OFF), the address counter 12 is cleared by the change from OFF to ON, and address 0 of the musical score memory 7 is designated. As a result, the pitch data and note length data stored at address 0 are output from e in the musical score memory 7. Also, turn on clear switch 13.
→Inverter 18 and OR gate 2 due to OFF change
4, the tone length counter 16 is operated, and tone length data is set in the tone length counter 16. Then, the musical tone forming section 14 forms musical tones based on the pitch data of the output e of the musical score memory 7. During this time, the note length counter 16 starts counting from the count value set based on the note length data and counts up the output clock of the tempo oscillator 15 until it reaches the maximum count value. When the tone length counter 16 counts the maximum count value, the tone length counter 16 outputs a counting end pulse. Therefore, the time period that the tone length counter 16 is counting corresponds to the tone length. When a counting end pulse is output to the output of the tone length counter 16,
This pulse is AND gate 21, OR gate 2
2 and 23 to the clock input CK of the address counter 12.

When this counting end pulse changes from a high level to a low level, the address counter 12 counts up by one step and specifies the first address of the musical score memory 7. In this way, 1 of musical score memory 7
The contents stored at the address, that is, the pitch data and the note length data are outputted to the output e of the musical score memory 7, respectively. Next, when the counting end pulse changes from low level to high level, the change is applied to note length counter 16 via AND gate 21 and OR gate 24, and the new note length output to the terminal of musical score memory 7 is changed. Set the data in the note length counter 16. Based on this tone length data, the tone length counter 16 counts the output clock of the tempo oscillator 15 and determines the tone length in the same manner as in the case of address 0. In this way, the contents of the musical score memory 7 are converted one after another into musical tones of a predetermined length.

Now, assuming that the score memory 7 is at address 20, 21
The part from address 50 will be skipped and the automatic performance will continue from address 51. First, the pause switch 9 is activated, a low level (ON) is sent from the pause switch 9 to the gate 21, the gate 21 is placed in a blocking state, and the counting end pulse from the tone length counter 16 is blocked. Press. Here, it is assumed that the frequency of the oscillator 11 is sufficiently higher than the average frequency of the counting end pulses. The fast-forward operation is the same as when programming. Since it is in automatic performance mode, musical tones are generated with a fixed length depending on the speed of fast forwarding. In addition, by allowing the user to change the oscillation frequency of the oscillator 11, which determines the fast-forward speed, the user can not only generate musical tones with a fixed length during automatic performance or fast-forward operations, but also freely change the length of the sound. can be changed to

By setting the frequency of the oscillator 11 to the normal automatic performance level and making the fast-forward switch 10 a lock type switch, and making it possible to change the oscillation frequency of the oscillator 11, you can not only automatically play a fixed musical score but also change the note length. By controlling the device, the user can play their own music with an original rhythm. Further, the address setting section 8
By using an up/down counter in the address counter 12 and providing an up/down changeover switch, automatic performance can be performed in the direction completely opposite to the normal direction. In other words, as usual, the direction of fast forwarding when specifying the address of the music score memory 7 is as follows: address 0 → address 1 → address 10 → address 11.
In addition to the 1 operation, by setting the up/down switch to the down side, it becomes possible to specify an address by 1, such as from address 50 to address 10. In this way, when the score memory 7 moves from address 10 to address 50 and performs automatic performance again from address 10,
For example, rather than returning from address 100 → address 0 → address 10 (address specification + 1 operation), address specification -
With one operation, you can quickly go back in the opposite direction from address 50 to address 10. Further, in the above explanation, the fast forward switch 10 and the pause switch 9 were independent, but it goes without saying that the same operation as above can be achieved even if they are linked. Furthermore, in the above explanation, the oscillator 11 was provided separately from the tempo oscillator 15, but
When pressing the fast-forward switch using the tempo oscillator 15, the oscillation frequency of the tempo oscillator 15 is switched to a higher frequency so that it can count at a time sufficiently faster than the normal note length (for example, if it is a CR oscillator, the resistor R is switched or Needless to say, the same operation as described above can be achieved by changing the value (the value may be changed).

Next, another embodiment of the present invention using a microcomputer will be described. FIG. 2 is a system block diagram of a microcomputer MN1400 manufactured by Matsushita Electronics Industries, Ltd. used in this example. As is well known, a microcomputer is a type of computer, and the exchange of signals is program-controlled using microinstructions. Although it is difficult to ensure a one-to-one correspondence between each functional block in Figure 1 and each part of the microcomputer,
The concept of the present invention itself does not change even if a microcomputer is used. For example, the code contents of pitch code converter 2 and tone length code converter 4 in FIG. 1 are stored in an internal read-on memory ROM. However, in this microcomputer, the contents of the internal ROM are transferred to the internal random access memory RAM as soon as the power is turned on, and the internal
Perform conversion in RAM area. The note length temporary storage means 5 in FIG. 1 is set in a predetermined area of the RAM.
Further, the tone length counter 16 corresponds to a built-in counter. In other words, the count data is stored in the RAM area, and the count data specified by the input is stored internally.
It is taken out from the RAM, exchanged between the performance unit (ALU) and the accumulator (ACC) (controlled by a program), and set in the built-in counter to perform the desired counting. In this way, the tone length counter 16 can be realized. Further, the address setting unit 8 stores the address currently being executed in the internal RAM area of the microcomputer, and exchanges address +1 operations, clear operations, etc. between the internal RAM area, address storage latch 29, ALU, and ACC. This can be achieved by The fast-forward operation uses the output signal of the tempo oscillator 15 (see Figure 3) connected to the SNSI input of the microcomputer 28, or the processor cycle of the microcomputer 28 to determine the fast-forward speed. and address storage latch 29, internal RAM area,
This can be achieved by exchanging data between ALU and ACC.

FIG. 3 shows another embodiment of the present invention using a microcomputer MN1400. First, the input and output configuration of the microcomputer will be explained. Pitch input section 1, pitch input section 3, P/A switch 6,
Switches such as the pause switch 9, clear switch 13, and fast forward switch 10 are connected to the output ports Coφ to Co6 and input ports of the microcomputer 28.
It is placed at each intersection of the matrix formed by Aiφ to Ai3 and Biφ to Bi3. Output port Coφ~
Output 7-phase pulses in order from Co6 and input port
The search results from Aiφ to Ai3 and Biφ to Bi3 are loaded into the microcomputer 28 and processed. In this way, it is determined which switch was pressed. Output ports Eoφ to Eo3 output pitch information, note length information, and address information of the musical score memory 7. And RAM 25 of music score memory 7,
The RAM 26 stores pitch information, and the RAM 27 stores note length information. Also, 4bits×2
The address of the musical score memory 7 is stored in the address storage latch 29 . Output port Co7 has music score memory 7
It outputs an R/W signal that determines whether to put it in a write state (W) or a read state (R). Output ports Co8 to Co10 have RAM, ,25,2
Outputs chip select signals 6 and 27. Output port Co11 outputs a write signal to address storage latch 29.

Regarding the operation, the operation explained in FIG.
This can be achieved by storing it in the ROM area and controlling it with a program.

As described above, according to the present invention, it is possible to fast-forward the address designation in the musical score memory by operating a single switch during programming or automatic performance.
Also, when programming a score, for example, if the capacity of the score memory is from 0 to 255 and you are currently programming at address 100, you notice that there is a mistake at address 50 and want to return to address 50. By operating the fast forward switch,
Address 100 → Address 255 → Address 0 → Address 50 (or 100
(address → address 80 → address 50), or operate the clear switch to set the music score memory address to address 0, then operate the fast forward switch to quickly return to address 50. In addition, during automatic performance, for example, if you want to perform automatic performance at address 50 in the score memory and skip addresses 51 to 100 and automatically play from address 101, you can quickly send it by operating the fast forward switch.
Furthermore, it has excellent advantages such as being able to continue playing automatically from address 101.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the invention, FIG. 2 is a system block diagram of a microcomputer, and FIG. 3 is a block diagram showing another embodiment of the invention using a microcomputer. 1...Pitch input section, 2...Pitch code conversion section,
3...Tone length input section, 4...Tone length code conversion section, 5
...Tone length temporary storage section, 6...P/A switch, 7
...Score memory, 8...Address specification section, 9...Pause switch, 10...Fast forward switch, 11...
Oscillator, 12...Address counter, 13...Clear switch, 14...Tone generator, 15...Tempo oscillator, 16...Tone length counter, 17, 18...
...Inverter, 19, 20, 21... AND gate that takes logical product, 22, 23, 24... OR gate that takes logical sum.

Claims (1)

[Claims] 1. A pitch input section that specifies the pitch of a musical tone, a pitch code conversion section that converts the pitch specified by the pitch input section into a predetermined code signal, and a pitch code conversion section that specifies the pitch of a musical tone. a tone length input section that specifies the tone length input section; a tone length code conversion section that converts the length of the musical tone specified by the tone length input section into a predetermined code signal; and output information of the pitch code conversion section and the tone length. a musical score memory that stores the output information of the code conversion section; a musical tone generation section that generates musical tones based on the output of the musical score memory; an address designation section that sequentially specifies the addresses of the musical score memory; and each of the above outputs to the musical score memory. A program for switching between a state of writing information and a state of reading out each of the output information stored in the score memory - an automatic performance switching member, and the address designation according to each note length from the score memory during automatic performance. a clock generator that sends a second clock signal to the address specifying section each time a pitch is specified from the pitch input section during program input; and a fast-forward control section that sends a third clock signal to the address designation section, and the operation of the fast-forward control section allows the address designation of the musical score memory to be controlled for each note length during automatic performance and for the operation of the pitch input section. The musical score memory addresses are sequentially specified at a frequency sufficiently higher than the average frequency of the output signal of the tone length counter regardless of the frequency, so that musical tones are generated with a constant tone length depending on the fast-forwarding speed. A programmable automatic performance device. 2. The programmable automatic performance device according to claim 1, wherein the address designation section is constituted by a counter. 3. In the programmable automatic performance device according to claim 1, the fast-forward control section includes an oscillation means for determining the fast-forward speed and a fast-forward control unit.
A programmable automatic performance device characterized by comprising a fast-forward switch for ON/OFF operation. 4. The programmable automatic performance device according to claim 3, wherein the oscillation means is configured to be able to change its oscillation frequency. 5. In the programmable automatic performance device according to claim 1, the address designation section is configured with an up-down counter, and the address designation section of the musical score memory can be operated by +1 and -1 for address designation by an up-down changeover switch. A programmable automatic performance device characterized by: 6. The programmable automatic performance device according to claim 3, wherein the oscillation means utilizes a processor cycle of a microcomputer. 7. In the programmable automatic performance device according to claim 1, the fast-forward control unit includes a tempo oscillator and a note length counter that determine the length of each note during automatic performance, and when fast-forwarding, the tempo oscillator A programmable automatic performance device characterized in that the oscillation frequency of the automatic performance device is changed to a frequency sufficiently higher than that during normal automatic performance.