JPS6243150A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6243150A JPS6243150A JP18251185A JP18251185A JPS6243150A JP S6243150 A JPS6243150 A JP S6243150A JP 18251185 A JP18251185 A JP 18251185A JP 18251185 A JP18251185 A JP 18251185A JP S6243150 A JPS6243150 A JP S6243150A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- melting point
- silicon
- point metal
- high melting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装１２゛ｔσ）配線層形成の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a manufacturing method for forming a wiring layer of a semiconductor device (12゛tσ).
本発明は、半導体装置の配線層形成の製造方法において
、絶縁膜にシリコン原子？イオン打ち込みした後、高融
点金属を蒸着することにより、高融点金属膜の絶縁膜と
の密着性を向上させる事である。The present invention provides a manufacturing method for forming a wiring layer of a semiconductor device, in which silicon atoms are added to an insulating film. After ion implantation, a high melting point metal is vapor-deposited to improve the adhesion of the high melting point metal film to the insulating film.
従来の半導体装置の配線形成方法は、絶縁膜上に、単に
高融点金属膜を蒸着しているのみであった。In the conventional method for forming wiring for semiconductor devices, a high melting point metal film is simply deposited on an insulating film.
〔発明が解決しようとする問題点及び目的〕しかし、前
述の従来技術では、絶縁膜と高融点金属膜との密着性が
悪いという問題点を有する。[Problems and Objects to be Solved by the Invention] However, the above-mentioned prior art has a problem in that the adhesion between the insulating film and the high melting point metal film is poor.
そこで本発明はこのような問題点を解決するもので、そ
の目的とするところは、密着性向上を提供するところに
ある。The present invention is intended to solve these problems, and its purpose is to provide improved adhesion.
本発明の半導体装置の製造方法は、絶縁膜にシリコン原
子をイオン打ち込みした後、高融点金属を蒸着すること
を特徴とする。The method for manufacturing a semiconductor device of the present invention is characterized in that silicon atoms are ion-implanted into an insulating film, and then a high-melting point metal is vapor-deposited.
本発明の上記の構成によれば、高融点金属、特に、タン
グステンを、六７ツ化タングステンを用いて、絶縁膜、
特に、シリコン酸化膜上に、蒸着する場合、蒸着時に、
シリコン酸化膜がエツチングされる事によりタングステ
ンが成長しにくいことや、シリコン酸化膜とタングステ
ンが反応しにくいため、密着性が低下する事が生じるが
、シリコン酸化膜の表面が、シリコン打ち込みによりシ
リコン過剰層になっているため、上記の問題は生じない
。According to the above configuration of the present invention, a high melting point metal, particularly tungsten, is used to form an insulating film using tungsten hexa7tride.
In particular, when depositing on a silicon oxide film, during deposition,
Etching of the silicon oxide film makes it difficult for tungsten to grow, and the silicon oxide film and tungsten do not easily react, resulting in a decrease in adhesion. Since it is layered, the above problem does not occur.
第１図は、本発明の実施例における製造方法の断面図で
あり、まず、第１図（α）の様に、半導体基板（１０１
）上に、絶縁膜（１０２）としてシリコン酸化膜ご形成
した後、シリコン打ち込み（１０３）を行なう。本実施
例では、シリコン原子を、加速エネルギー４０にθＶ、
打ち込みｊ１７）＜１０１１〆２で行なった。その後、
第１図（ｂ）の様に、イオン打ち込みの結果、シリコン
過剰層（１０４）となった上に、タングステンを、六７
ツ化タングステン６０ ｏｅ−ｍ 、水素５００工／調
流し、温度５００℃で蒸着した。FIG. 1 is a cross-sectional view of a manufacturing method in an embodiment of the present invention. First, as shown in FIG. 1 (α), a semiconductor substrate (101
), a silicon oxide film is formed as an insulating film (102), and then silicon implantation (103) is performed. In this example, silicon atoms are accelerated at an acceleration energy of 40 V,
Input j17) <1011〆2. after that,
As shown in FIG. 1(b), tungsten is added to the excess silicon layer (104) as a result of ion implantation.
Vapor deposition was carried out using 60 oe-m of tungsten fluoride, 500 cycles/controlled flow of hydrogen, and a temperature of 500°C.
以上述べたように発明によれば、絶ｍｌに、シリコン原
子をイオン打ち込みし、絶縁膜表面に、シリコン過剰層
をつくる事により、その上部に形成する高融点金属の絶
縁膜との密着性が向上するという効果を有する。As described above, according to the invention, silicon atoms are ion-implanted in an absolutely perfect amount to form an excess silicon layer on the surface of the insulating film, thereby improving the adhesion with the high-melting point metal insulating film formed on top of the silicon-excess layer. It has the effect of improving
第１図（α）＋（ｈ）は、本発明の半導体装置の製造方
法の断面図。
１０１・・・・・・半導体基板
１０２・・・・・・絶縁膜
１０３・・・・・・シリコン打ち込み
１０４・・・・・・シリコン過剰層
１０５・・・・・・高融点金属FIG. 1(α)+(h) is a cross-sectional view of the method for manufacturing a semiconductor device of the present invention. 101...Semiconductor substrate 102...Insulating film 103...Silicon implantation 104...Silicon excess layer 105...High melting point metal
Claims (3)
絶縁膜にシリコン原子をイオン打ち込みした後、高融点
金属を蒸着する事を特徴とする半導体装置の製造方法。(1) In a manufacturing method for forming a conductive film on an insulating film,
A method for manufacturing a semiconductor device characterized by ion-implanting silicon atoms into an insulating film and then depositing a high melting point metal.
する特許請求の範囲第１項記載の半導体装置の製造方法
。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is a silicon oxide film.
とする特許請求の範囲第１項記載の半導体装置の製造方
法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein the high melting point metal is tungsten.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18251185A JPS6243150A (en) | 1985-08-20 | 1985-08-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18251185A JPS6243150A (en) | 1985-08-20 | 1985-08-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6243150A true JPS6243150A (en) | 1987-02-25 |
Family
ID=16119575
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18251185A Pending JPS6243150A (en) | 1985-08-20 | 1985-08-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6243150A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5882961A (en) * | 1995-09-11 | 1999-03-16 | Motorola, Inc. | Method of manufacturing semiconductor device with reduced charge trapping |
| KR100253561B1 (en) * | 1992-08-28 | 2000-05-01 | 김영환 | Method of depositing w on oxide of semiconductor device without adhesion layer |
-
1985
- 1985-08-20 JP JP18251185A patent/JPS6243150A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100253561B1 (en) * | 1992-08-28 | 2000-05-01 | 김영환 | Method of depositing w on oxide of semiconductor device without adhesion layer |
| US5882961A (en) * | 1995-09-11 | 1999-03-16 | Motorola, Inc. | Method of manufacturing semiconductor device with reduced charge trapping |
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