JPS6242530B2 - - Google Patents

Info

Publication number
JPS6242530B2
JPS6242530B2 JP55108565A JP10856580A JPS6242530B2 JP S6242530 B2 JPS6242530 B2 JP S6242530B2 JP 55108565 A JP55108565 A JP 55108565A JP 10856580 A JP10856580 A JP 10856580A JP S6242530 B2 JPS6242530 B2 JP S6242530B2
Authority
JP
Japan
Prior art keywords
time
reception
interruption
frequency
current station
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55108565A
Other languages
Japanese (ja)
Other versions
JPS5732139A (en
Inventor
Seiichiro Hirata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10856580A priority Critical patent/JPS5732139A/en
Priority to US06/288,199 priority patent/US4414687A/en
Priority to SE8104605A priority patent/SE454035B/en
Priority to DE19813130863 priority patent/DE3130863A1/en
Publication of JPS5732139A publication Critical patent/JPS5732139A/en
Publication of JPS6242530B2 publication Critical patent/JPS6242530B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03JTUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J1/00Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general
    • H03J1/0008Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor
    • H03J1/0041Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor for frequency synthesis with counters or frequency dividers
    • H03J1/005Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor for frequency synthesis with counters or frequency dividers in a loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Superheterodyne Receivers (AREA)
  • Circuits Of Receivers In General (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Description

【発明の詳細な説明】 この発明は受信機に関し、特に、カーラジオな
どにおいて、或る放送局の電波を受信しながら他
の放送局の電波の受信状態を検知するような受信
機に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiver, and particularly to a receiver such as a car radio that detects the reception state of radio waves of other broadcast stations while receiving radio waves of a certain broadcast station.

たとえばカーラジオなどの車に搭載されている
受信機において、たとえばFM放送を受信する場
合、ある放送局のサービスエリア内においては正
常にその放送電波を受信することができるが、そ
のサービスエリア外になると良好に放送電波を受
信することができない。この場合、それまでに受
信していた放送局にかえて受信状態の良好な他の
放送局の電波を選局する必要がある。したがつ
て、受信状態が悪くなる度に選局のための操作を
しなければならない。
For example, when receiving FM broadcasts using a receiver installed in a car, such as a car radio, it is possible to receive the broadcast waves normally within the service area of a certain broadcast station, but when outside the service area, If this happens, you will not be able to receive broadcast waves well. In this case, it is necessary to select the radio waves of another broadcasting station with good reception status instead of the broadcasting station that was being received up to that point. Therefore, it is necessary to perform an operation to select a channel every time the reception condition becomes poor.

ところで、ヨーロツパなどにおいては、異なる
周波数で同一のプログラムを放送する放送局が分
散されて配置されているところがある。このよう
な地域では、或る放送局の放送電波を受信しなが
ら、同一のプログラムを放送しかつ周波数の異な
る他の放送局の放送電波の受信状態を検知し、現
在受信している放送電波の受信状態が悪くなつた
とき、受信状態の良好な他の放送電波に切換える
ことが考えられる。
By the way, in Europe and the like, there are places where broadcasting stations that broadcast the same program on different frequencies are distributed. In such areas, while receiving the airwaves of a certain broadcasting station, the reception status of the airwaves of other broadcasting stations broadcasting the same program but with different frequencies is detected, and the reception status of the airwaves of other broadcasting stations that are broadcasting the same program but on a different frequency is detected. When reception conditions become poor, it is conceivable to switch to another broadcast wave with better reception conditions.

そこで、カーラジオに2系統のチユーナを内蔵
し、一方のチユーナをある放送局の放送電波に同
調させ、他方のチユーナを他の放送局の放送電波
に同調させて受信状態を検知する方式が考えられ
ている。しかしながら、1台のカーラジオに2系
統のチユーナを内蔵させるとコスト的に高くなつ
てしまいかつ大形化する。また、1つのアンテナ
で2系統の電波を受信することになり、アンテナ
感度が劣化するという問題点があつた。
Therefore, a method has been proposed in which two tuners are built into the car radio, one tuner is tuned to the broadcast waves of a certain broadcasting station, and the other tuner is tuned to the broadcast waves of another broadcast station to detect the reception status. It is being However, if two tuners are built into one car radio, the cost becomes high and the radio becomes large. In addition, one antenna receives two systems of radio waves, resulting in a problem that the antenna sensitivity deteriorates.

この問題点を解決するために、1つのチユーナ
を含む受信機である放送局の放送電波を受信しな
がら、極めて短い時間だけその放送電波の受信を
中断して、その時間の間に他の放送局の放送電波
の受信状態を検知する方法が考えられ。この場合
の中断する時間は、極めて短かくしなければ、人
間の聴覚上不快感を与えてしまう。
In order to solve this problem, the receiver including one tuner, while receiving the broadcast waves of a broadcast station, interrupts the reception of the broadcast waves for a very short period of time, and during that time, listens to other broadcasts. One possible method is to detect the reception status of the station's broadcast waves. The interruption time in this case must be extremely short, otherwise it will cause discomfort to human hearing.

ところで、最近のカーラジオでは、その局部発
振回路に位相同期ループ(PLL)を有するデイジ
タル周波数シンセイザを用いたものが多い。この
ようなPLLはロツクするまでの時間を短くする
と、ジツタが増加するという欠点を有するため、
極めて短い時間の間に現在受信している放送局の
放送電波の周波数から他の放送局の電波の周波数
にロツクすることができなかつた。
Incidentally, many recent car radios use digital frequency synthesizers having a phase-locked loop (PLL) in their local oscillation circuits. This type of PLL has the disadvantage that jitter increases when the time to lock is shortened, so
It was not possible to lock from the frequency of the broadcast radio waves of the currently received broadcasting station to the frequency of radio waves of another broadcast station within an extremely short period of time.

それゆえに、この発明の主たる目的は、位相同
期ループを有するデイジタル周波数シンセサイザ
を局部発振回路に含む受信機において、現在受信
している周波数の受信を極めて短時間で周期的に
中断させると共に、その中断中における周波数を
切換えるときのロツクする時間を極めて短かくし
得る受信機を提供することである。
Therefore, the main object of the present invention is to periodically interrupt the reception of the currently received frequency in an extremely short period of time in a receiver including a digital frequency synthesizer having a phase-locked loop in its local oscillator circuit, and to An object of the present invention is to provide a receiver that can extremely shorten the locking time when switching frequencies within the receiver.

この発明は、要約すれば、現在受信している周
波数の受信を極めて短時間で周期的に中断させる
と共に、その中断中における受信周波数を切換え
るとき、位相同期ループの時定数を小さくして、
切換えられた受信周波数にロツクするまでの時間
を短かくするようにしたものである。
To summarize, this invention periodically interrupts the reception of the currently received frequency in an extremely short period of time, and when switching the receiving frequency during the interruption, reduces the time constant of the phase-locked loop.
This shortens the time it takes to lock onto the switched reception frequency.

この発明の上述の目的およびその他の目的と特
徴は以下に図面を参照して行なう詳細な説明から
一層明らかとなろう。
The above objects and other objects and features of the present invention will become more apparent from the detailed description given below with reference to the drawings.

第1図はこの発明の一実施例のブロツク図であ
り、第2図は第1図に含まれるループフイルタの
具体的な電気回路図である。
FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a specific electrical circuit diagram of the loop filter included in FIG. 1.

構成において、受信手段はアンテナ1と高周波
増幅器2と周波数混合器3と中間周周波増幅器4
と検波器5とミユーテイング回路6と低周波増幅
器7とスピーカ8とから構成される。このような
受信手段はスーパヘテロダイン方式の受信機とし
て周知のものであるため、その具体的な説明は省
略する。周波数混合器3に関連して、電圧制御発
振器9と分周器10と位相検波器11と基準発振
器13とループフイルタ12とから構成される
PLLを含む周波数シンセサイザ回路が設けられ
る。受信状態信号検知器15は、同一プログラム
を放送している他の周波数の放送局の受信レベル
を検知するものである。
In the configuration, the receiving means includes an antenna 1, a high frequency amplifier 2, a frequency mixer 3, and an intermediate frequency amplifier 4.
It is composed of a wave detector 5, a muting circuit 6, a low frequency amplifier 7, and a speaker 8. Since such receiving means is well known as a superheterodyne receiver, a detailed explanation thereof will be omitted. In relation to the frequency mixer 3, it is composed of a voltage controlled oscillator 9, a frequency divider 10, a phase detector 11, a reference oscillator 13, and a loop filter 12.
A frequency synthesizer circuit including a PLL is provided. The reception status signal detector 15 detects the reception level of broadcast stations on other frequencies that are broadcasting the same program.

制御装置14はたとえばマイクロコンピユータ
などによつて構成され、ミユーテイング回路6に
極めて短いパルス信号を与えるとともに、分周器
10に対して分周比のデータを与える。また、制
御装置14は極めて短い時間期間、PLLのロツク
を速めるためにループフイルタ12に対してルー
プ帯域切換信号cを与える。
The control device 14 is constituted by, for example, a microcomputer, and provides an extremely short pulse signal to the muting circuit 6, and also provides frequency division ratio data to the frequency divider 10. The controller 14 also provides a loop band switching signal c to the loop filter 12 for a very short period of time to speed up the locking of the PLL.

ループフイルタ12は第2図に示すように、抵
抗R1とR2と演算増幅器17との直列回路から
なり、演算増幅器17の入力端と出力端との間に
は抵抗R3とコンデンサCとの直列回路が接続さ
れる。また、前記制御装置14からループ帯域切
換信号が与えられたとき、その接点が閉じるアナ
ログスイツチ16が抵抗R1に対して並列接続さ
れる。そして、ループ帯域切換信号が与えられた
とき、アナログスイツチ16が閉じて抵抗R1を
短絡し、PLLのループ時定数を小さくする。
As shown in FIG. 2, the loop filter 12 consists of a series circuit of resistors R1 and R2 and an operational amplifier 17, and a series circuit of a resistor R3 and a capacitor C is connected between the input and output ends of the operational amplifier 17. is connected. Further, an analog switch 16 whose contact closes when a loop band switching signal is applied from the control device 14 is connected in parallel to the resistor R1. When the loop band switching signal is applied, the analog switch 16 closes to short-circuit the resistor R1, thereby reducing the loop time constant of the PLL.

第3図ないし第6図は第1図および第2図の動
作を説明するための波形図である。
FIGS. 3 to 6 are waveform diagrams for explaining the operations of FIGS. 1 and 2.

次に、第1図ないし第6図を参照してこの発明
の一実施例の具体的な動作について説明する。制
御装置14は、ある放送局(以下、現在局と称す
る)の放送電波を受信しているとき、第3図に示
すように一定の周期T2毎に極めて短いパルス幅
T1を有するパルス信号aをミユーテイング回路
6に与える。ミユーテイング回路6は、このパル
ス信号aが与えられたことに応じて、パルス期間
T1だけ第4図に示すようにその音声出力信号を
減衰させる。この音声を減衰させる時間T1は
種々の実験結果によると、5msec以下であり、そ
の周期T2は約0.5sec以上であれば、たとえ放送
電波を受信中であつても、人間の聴感に全く障害
を与えることがない。
Next, the specific operation of one embodiment of the present invention will be explained with reference to FIGS. 1 to 6. When the control device 14 is receiving broadcast waves from a certain broadcasting station (hereinafter referred to as the current station), the control device 14 sends out a pulse signal a having an extremely short pulse width T1 at a constant period T2, as shown in FIG. It is applied to the mutating circuit 6. In response to being supplied with this pulse signal a, the muting circuit 6 attenuates its audio output signal by a pulse period T1 as shown in FIG. 4. According to various experimental results, the time T1 for attenuating this sound is 5 msec or less, and if the period T2 is approximately 0.5 sec or more, there will be no disturbance to human hearing even when receiving broadcast radio waves. I have nothing to give.

同時に、制御装置14は他の放送電波を受信手
段に受信させるために、制御線bを介して他の放
送局の電波を受信するのに必要な分周比データを
分周器10に与える。また、ループフイルタ12
に対してループ帯域切換信号cを与える。この信
号cが与えられたことにより、第2図に示すアナ
ログスイツチ16がオンして抵抗R1の両端が短
絡される。
At the same time, the control device 14 provides frequency division ratio data necessary for receiving the radio waves of other broadcasting stations to the frequency divider 10 via the control line b in order to cause the receiving means to receive the other broadcast radio waves. In addition, the loop filter 12
A loop band switching signal c is applied to the loop band switching signal c. When this signal c is applied, the analog switch 16 shown in FIG. 2 is turned on, and both ends of the resistor R1 are short-circuited.

すなわち、ループフイルタの時定数が小さくさ
れる。それによつて、位相検波器11、ループフ
イルタ12、電圧制御発振器9および分周器10
によるPLLのロツクが速められ、電圧制御発振器
9は分周器10に設定された分周比に基づく局部
発振周波数を発生する。この局部発振周波数が周
波数混合器3に与えられる。それによつて、受信
手段が現在局にかえて他の周波数の放送局を受信
する。受信された電波の受信レベルは受信状態信
号検知器15によつて検知される。なお、それま
でに受信していた現在局の受信レベルは、たとえ
ばメモリ(図示せず)に記憶されていて、受信状
態信号検知器15が検知した受信レベルとメモリ
に記憶していた現在局の受信レベルとが比較回路
(図示せず)によつて比較される。そして、制御
回路14は現在局の受信レベルが他の放送局の受
信レベルよりも高ければ、再び分周器10に対し
て現在局を受信するための分周比データを与え
る。応じて、PLLはその分周比に基づいてロツク
し、電圧制御発振器9がその分周比に対応した局
部発振周波数を発生して周波数混合器3に与え
る。
That is, the time constant of the loop filter is reduced. Thereby, phase detector 11, loop filter 12, voltage controlled oscillator 9 and frequency divider 10
The locking of the PLL by the voltage control oscillator 9 is accelerated, and the voltage controlled oscillator 9 generates a local oscillation frequency based on the division ratio set in the frequency divider 10. This local oscillation frequency is applied to the frequency mixer 3. Thereby, the receiving means receives a broadcast station of another frequency instead of the current station. The reception level of the received radio waves is detected by the reception status signal detector 15. The reception level of the current station that has been received up to that point is stored, for example, in a memory (not shown), and the reception level detected by the reception status signal detector 15 and the reception level of the current station stored in the memory are stored. The received level is compared by a comparison circuit (not shown). Then, if the reception level of the current station is higher than the reception level of other broadcast stations, the control circuit 14 again provides frequency division ratio data for receiving the current station to the frequency divider 10. In response, the PLL locks based on the frequency division ratio, and the voltage controlled oscillator 9 generates a local oscillation frequency corresponding to the frequency division ratio and supplies it to the frequency mixer 3.

このように、ある放送局を受信しているとき
に、その受信を中断して他の放送局の電波を受信
し、再び現在局の受信に戻るまでの時間T3が時
間T1以下となるようにPLLを形成する必要があ
る。そのために、この実施例では、前期時間T3
の間はPLLの時定数を小さくしている。すなわ
ち、制御装置14から第6図に示すようなT4の
パルス幅を有するループ帯域切換信号cをアナロ
グスイツチ16に与えて、時間T4の間だけ抵抗
R1の両端を短絡している。
In this way, when receiving a certain broadcast station, the time T3 required to interrupt the reception, receive the radio waves of another broadcast station, and return to receiving the current station is less than the time T1. It is necessary to form a PLL. Therefore, in this embodiment, the first period T3
During this period, the PLL time constant is made small. That is, a loop band switching signal c having a pulse width of T4 as shown in FIG. 6 is applied from the control device 14 to the analog switch 16 to short-circuit both ends of the resistor R1 only for a time T4.

ここで、PLLを、数式を用いて解析すると、一
般にPLLは、 ωo:自然角周波数 ξ:ダンピング定数 Ko:電圧制御発振器ゲイン Kd:位相検波器感度 τ:R2Cまたは(R1+R2)C τ:R3C 前述の第(1)式および第(2)式から明らかなよう
に、自然角周波数ωoが大きくなれば、PLLの引
込時間が速くなるが、電圧制御発振器9のジツタ
が大きくなる。逆に、ωoが小さくなれば引込時
間は遅くなるが、電圧制御発振器9のジツタは小
さくなる。電圧制御発振器9は周波数混合器3の
局部発振器として作用するため、電圧制御発振器
9のジツタが大きくなれば受信SN比が劣化す
る。このために、この実施例では、ループ帯域切
換信号cのパルス幅T4の間だけωoを大きくし
て引込時間を速くすることにより、T3<T1を
充分に満足できるようにしている。そして、時間
T4以外ではωoを小さくして電圧制御発振器9
のジツタを最小限に抑えている。時間T4の間は
電圧制御発振器9のジツタによつて受信手段の
SN比が悪くなるが、この期間中は制御装置14
から、ミユーテイング回路6にミユーテイング信
号aが与えられている。したがつて、時間T1の
期間だけ音声出力が減衰されるので、聴感上聞き
若しくなることはない。また、ミユーテイング信
号aが与えられていない間はループ帯域切換信号
cも与えられないので、アナログスイツチ16が
開かれ、抵抗R1が有効化される。したがつて、
時間T1の期間を除いてωoを小さくすることが
できるので、SN比の良好な状態で常に特定の放
送局の放送電波を受信することができる。
Here, when PLL is analyzed using mathematical formulas, PLL generally becomes ω o : Natural angular frequency ξ : Damping constant Ko : Voltage controlled oscillator gain Kd : Phase detector sensitivity τ 1 : R 2 C or (R 1 + R 2 ) C τ 2 : R 3 C Equation (1) and As is clear from equation (2), as the natural angular frequency ω o increases, the PLL pull-in time becomes faster, but the jitter of the voltage controlled oscillator 9 increases. Conversely, as ω o becomes smaller, the pull-in time becomes slower, but the jitter of the voltage controlled oscillator 9 becomes smaller. Since the voltage controlled oscillator 9 acts as a local oscillator for the frequency mixer 3, if the jitter of the voltage controlled oscillator 9 increases, the reception SN ratio will deteriorate. For this reason, in this embodiment, ωo is increased only during the pulse width T4 of the loop band switching signal c to speed up the pull-in time, so that T3<T1 can be fully satisfied. Then, at times other than time T4, ω o is made small and the voltage controlled oscillator 9
jitter is kept to a minimum. During time T4, the jitter of the voltage controlled oscillator 9 causes the receiving means to
Although the SN ratio deteriorates, during this period the control device 14
, a muting signal a is given to the muting circuit 6. Therefore, since the audio output is attenuated for the period of time T1, the audio does not become audible. Furthermore, since the loop band switching signal c is not applied while the muting signal a is not applied, the analog switch 16 is opened and the resistor R1 is enabled. Therefore,
Since ω o can be made small except for the period of time T1, it is possible to always receive broadcast waves from a specific broadcasting station with a good signal-to-noise ratio.

なお、ミユーテイング回路6は必ずしも必要な
ものではなく、単に現在局を受信している間に、
他の放送電波の受信状態を検知するだけであるな
らばこのミユーテイング回路6を除去してもよ
い。
It should be noted that the muting circuit 6 is not necessarily necessary, and merely transmits the message while receiving the current station.
This muting circuit 6 may be removed if only the reception state of other broadcast waves is to be detected.

以上のように、この発明によれば、現在受信し
ている周波数の受信を極めて短時間で周期的に中
断させると共に、その中断中における受信周波数
を切換えるときに、位相同期ループの時定数を小
さくするようにしているため、切換えるべき周波
数にロツクする時間を極めて短かくすることがで
き、聴覚上の不快感を生じることなく、放送電波
を受信中に他の局の放送電波の受信状態を検知す
ることが可能になる。
As described above, according to the present invention, reception of the currently received frequency is periodically interrupted in an extremely short period of time, and when switching the receiving frequency during the interruption, the time constant of the phase-locked loop is reduced. This makes it possible to extremely shorten the time it takes to lock on to the frequency to be switched to, and to detect the reception status of other stations' broadcast waves while receiving broadcast waves without causing auditory discomfort. It becomes possible to do so.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例のブロツク図であ
る。第2図は第1図に含まれるループフイルタの
具体的な回路図である。第3図、第4図、第5図
および第6図は第1図および第2図の動作を説明
するための波形図である。 図において1はアンテナ、2は高周波増幅器、
3は周波数混合器、4は中間周波増幅器、5は検
波器、6はミユーテイング回路、7は低周波増幅
器、8はスピーカ、9は電圧制御発振器、10は
分周器、11は位相検波器、12はループフイル
タ、16はアナログスイツチ、13は基準発振
器、14は制御装置、15は受信状態信号検知
器、R1,R2,R3は抵抗を示す。
FIG. 1 is a block diagram of one embodiment of the present invention. FIG. 2 is a specific circuit diagram of the loop filter included in FIG. 1. FIGS. 3, 4, 5 and 6 are waveform diagrams for explaining the operations of FIGS. 1 and 2. In the figure, 1 is an antenna, 2 is a high frequency amplifier,
3 is a frequency mixer, 4 is an intermediate frequency amplifier, 5 is a wave detector, 6 is a muting circuit, 7 is a low frequency amplifier, 8 is a speaker, 9 is a voltage controlled oscillator, 10 is a frequency divider, 11 is a phase detector, 12 is a loop filter, 16 is an analog switch, 13 is a reference oscillator, 14 is a control device, 15 is a reception status signal detector, and R1, R2, and R3 are resistors.

Claims (1)

【特許請求の範囲】 1 位相同期ループを有する周波数シンセサイザ
回路をその局部発振器に含む受信機において、現
在局の受信を極めて短い時間間隔で所定周期毎に
中断させ、この中断時に上記周波数シンセサイザ
回路が他の周波数の電波を受信し得るように制御
すると共に、上記中断時に受信した他の周波数の
受信レベルと現在局の受信レベルとの比較結果に
もとづいて受信レベルの高い局を上記現在局とし
て受信を継続するように上記周波数シンセサイザ
回路を制御する制御装置を備えたことを特徴とす
る受信機。 2 現在局の受信の中断の時間が5msec以下であ
り、中断の周期が0.5sec以上であることを特徴と
する特許請求の範囲第1項記載の受信機。 3 位相同期ループがループフイルタを有してお
り、現在局の受信の中断時に上記ループフイルタ
の時定数を切り換えて小さく設定することによ
り、切り換えるべき周波数にロツクする時間を短
くするようにしたことを特徴とする特許請求の範
囲第1項又は第2項に記載の受信機。 4 位相同期ループを有する周波数シンセサイザ
回路をその局部発振器に含む受信機において、現
在局の受信を極めて短い時間間隔で所定周期毎に
中断させ、この中断時に上記周波数シンセサイザ
回路が他の周波数の電波を受信し得るように制御
すると共に、上記中断時に受信した他の周波数の
受信レベルと現在局の受信レベルとの比較結果に
もとづいて受信レベルの高い局を上記現在局とし
て受信を継続するように上記周波数シンセサイザ
回路を制御する制御装置、および上記制御装置か
ら上記受信中断時に上記中断の時間間隔のパルス
信号を受けて、上記中断時の音声出力信号を減衰
させる回路を備えたことを特徴とする受信機。
[Claims] 1. In a receiver whose local oscillator includes a frequency synthesizer circuit having a phase-locked loop, the reception of the current station is interrupted every predetermined period at extremely short time intervals, and at the time of the interruption, the frequency synthesizer circuit is activated. Control is performed so that radio waves of other frequencies can be received, and a station with a high reception level is received as the current station based on the comparison result of the reception level of the other frequency received at the time of the interruption and the reception level of the current station. A receiver comprising a control device that controls the frequency synthesizer circuit so as to continue the frequency synthesizer circuit. 2. The receiver according to claim 1, wherein the reception interruption time of the current station is 5 msec or less, and the interruption cycle is 0.5 sec or more. 3. The phase-locked loop has a loop filter, and when the reception of the current station is interrupted, the time constant of the loop filter is switched and set to a smaller value, thereby shortening the time it takes to lock onto the frequency to be switched. A receiver according to claim 1 or 2. 4. In a receiver whose local oscillator includes a frequency synthesizer circuit having a phase-locked loop, the reception of the current station is interrupted every predetermined period at extremely short time intervals, and at the time of interruption, the frequency synthesizer circuit transmits radio waves of other frequencies. In addition, based on the result of comparison between the reception level of other frequencies received at the time of the interruption and the reception level of the current station, the station with the higher reception level is controlled to continue reception as the current station. A receiver comprising: a control device that controls a frequency synthesizer circuit; and a circuit that receives a pulse signal at the time interval of the interruption when the reception is interrupted from the control device, and attenuates the audio output signal at the time of the interruption. Machine.
JP10856580A 1980-08-04 1980-08-04 Receiver Granted JPS5732139A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP10856580A JPS5732139A (en) 1980-08-04 1980-08-04 Receiver
US06/288,199 US4414687A (en) 1980-08-04 1981-07-29 Radio receiver
SE8104605A SE454035B (en) 1980-08-04 1981-07-30 RADIORECEIVER
DE19813130863 DE3130863A1 (en) 1980-08-04 1981-08-04 BROADCAST RECEIVER

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10856580A JPS5732139A (en) 1980-08-04 1980-08-04 Receiver

Publications (2)

Publication Number Publication Date
JPS5732139A JPS5732139A (en) 1982-02-20
JPS6242530B2 true JPS6242530B2 (en) 1987-09-09

Family

ID=14488041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10856580A Granted JPS5732139A (en) 1980-08-04 1980-08-04 Receiver

Country Status (1)

Country Link
JP (1) JPS5732139A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6427308A (en) * 1988-07-08 1989-01-30 Mitsubishi Electric Corp On-vehicle receiver

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5577242A (en) * 1978-12-05 1980-06-10 Clarion Co Ltd Channel selection control system for frequency synthesizer receiver

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5252488Y2 (en) * 1972-10-14 1977-11-29

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5577242A (en) * 1978-12-05 1980-06-10 Clarion Co Ltd Channel selection control system for frequency synthesizer receiver

Also Published As

Publication number Publication date
JPS5732139A (en) 1982-02-20

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