JPS6242282B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a constant voltage circuit using an insulated gate field effect transistor (hereinafter referred to as IGFET). Conventionally, there is a method of outputting a low voltage from a high power supply voltage by causing a voltage drop using a current flowing through a resistor _R1 , as shown in FIG. 1, in order to lower the voltage. The voltage V ₀ generated at the output terminal 3 in response to load fluctuations in the load 1 and voltage fluctuations in the supply power terminal 2 is expressed by V ₀ =V _GG −R _{1 IL} . However, I _L is the current flowing to the load, and V _GG is the voltage at the supply power terminal 2.

Therefore, load fluctuations and fluctuations in the supply voltage directly result in fluctuations in the output voltage, resulting in a drawback that a stable voltage cannot be generated.

The aim of the invention is to eliminate the above-mentioned drawbacks and to
The present invention provides a constant voltage circuit that generates a stable output voltage in response to power fluctuations, etc.

The constant voltage circuit of the present invention includes an IGFET whose drain is connected to one end of a power supply and whose source is connected to an output terminal, and a one- or odd-stage inverter circuit consisting of an IGFET whose input is connected to the output terminal and whose output is connected to the gate of the IGFET. It supplies and outputs a constant voltage to the load connected to the output terminal. That is, in the constant voltage circuit of the present invention, changes in the current flowing through the IGFET connected between the power supply and the output terminal,
Or by detecting the voltage change at the output terminal using one or an odd number of stages of inverters, and using the inverter output as the gate input of the above IGFET.
The current or source output of the IGFET is controlled to obtain a constant voltage.

According to the present invention, in an integrated circuit, the constant voltage circuit of the present invention is configured together with a logic circuit on the same chip, and the constant voltage circuit of the present invention is used as a power source for a clock generator or a clock oscillator necessary for operating the logic circuit or shift register. By supplying the output of a constant voltage circuit, the minimum voltage necessary for the circuit to operate is stably generated against circuit load fluctuations and supply voltage fluctuations, so the speed/power product in the circuit is reduced. can be minimized. That is,
It is possible to always supply the optimum voltage for circuit operation. Therefore, it is possible to provide a high-speed integrated circuit with low power consumption. In addition, even for MOSFETs with short channel lengths that are at risk of being destroyed due to punch-through, the minimum low voltage required by the MOSFET is supplied, and punch-through does not occur. shellfish
MOSFET can be used, reducing chip size.

Therefore, a high density, high speed, low power consumption, and low cost integrated circuit can be provided. The inventor of the present application has developed a similar circuit in Japanese Patent Application No. 51-28352.
49885), but in contrast, the present invention provides IGFETQ ₄ and Q ₉ , so that only the sum voltage due to the threshold of this transistor and the rise in the source potential of the input transistor due to this threshold is output. This has the advantage that the constant voltage can be increased.

Hereinafter, the present invention will be explained based on examples.

FIG. 2 shows an embodiment of the present invention, in which Q ₁ , Q ₃ ,
Q ₆ , Q ₈ are depletion type MOSFETs, Q ₂ ,
Q ₄ , Q ₅ , Q ₇ are enhancement type MOSFETs, 4
For example, 5 is a logic circuit section, 5 is an external power supply terminal, and 6 is a logic circuit section.
7 is a generated voltage terminal and a power supply terminal of the logic circuit section, and 7 is an output terminal of an inverter composed of Q ₇ and Q ₈ . Q ₂ and Q ₃ and Q ₄ , Q ₅ and Q ₆ , and Q ₇ and Q ₈ each form an odd-stage inverter, and the gate and drain of Q ₄ are connected to the source of Q ₂ , and Q ₄
The source of is connected to a reference potential (ground). The drain of Q ₂ is connected to the source and gate of Q ₃ and the gate of Q ₅ , the output of the inverter of Q ₅ and Q ₆ is connected to the gate of Q ₇ , and the output of the inverter of Q ₇ and Q ₈ is connected to the gate electrode of depletion MOSFET Q ₁ . are connected. 1
In the case of stages, connect the outputs of Q ₂ and Q ₃ to the gate of Q ₁ . Further, the source electrode of Q ₁ is connected to the source electrode of Q ₂ and the power supply terminal 6 of the logic circuit section. Also
The drains of Q ₁ , Q ₃ , Q ₆ , and Q ₈ are connected to the power supply terminal 5. The inverters Q ₅ and Q ₆ and Q ₇ and Q ₈ have very large gm ratios of the drive transistors Q ₅ and Q ₇ and the load transistors Q ₆ and Q ₈ , respectively.
The output changes significantly in response to small changes in the gate voltage of _Q2 .

Also, Q ₃ , Q ₆ , and Q ₈ may be connected to a different power source than Q ₁ .

Figure 3 shows the depression type shown in Figure 2.
Voltage V _D at the source electrode of the MOSFET, that is, terminal 6
3 is a graph showing the characteristics of the current flowing through _Q1 , that is, the current I _L flowing through the logic circuit section, with respect to _D. I ₀ , I ₁ ,
I ₂ is the current value flowing due to load fluctuation in the logic circuit section. V _GG is the voltage at the external power supply terminal 5.

Figure 4 shows the input/output characteristics of a cascade-connected three-stage inverter consisting of Q ₄ , Q ₂ and Q ₃ , Q ₅ and Q ₆ , and Q ₇ and Q ₈ . The output changes significantly even with small fluctuations.
V _DD is the voltage at terminal 6, that is, the input voltage of Q ₂ , and V _G is
This is the inverter output voltage of Q ₇ and Q ₈ and is also the gate voltage of Q ₁ . Enhancement type IGFET
The threshold voltage of Q ₂ , Q ₄ , Q ₅ , Q ₇ is set to V
Assuming _TE , in order for Q ₂ and Q ₄ to turn on, the gate voltage of Q ₂ must be greater than 2V _TE + ΔV _TE (ΔV _TE is the increase in threshold voltage due to the backgate effect of Q ₂ ), so Q ₂ , The inverting input voltage V _DD of the inverter of Q ₄ and Q ₃ is greater than 2V _TE +ΔV _TE and is determined by the gm ratio of Q ₂ , Q ₄ and Q ₃ . Therefore, the output 7 of the three-stage inverter connected in series is
When the gate voltage of Q ₂ becomes a voltage determined by the gm ratio of Q ₂ , Q ₄ and Q ₃ with a value larger than ΔV _TE than 2V _TE , the output voltage V _G changes greatly.

The operating principle will be explained with reference to FIGS. 2, 3, and 4. Now, assume that a load current _I0 is flowing through the logic circuit section and the voltage _VDD at terminal 6 is _V0 . Fourth
From the figure, the value of V _G with respect to V ₀ is V _G0 , and this voltage is applied to the gate electrode of _Q1 . 8 is Q ₁
6 is a graph showing the relationship between voltage V _DD and load current I _L when a voltage V _G0 is applied to the gate electrode of FIG.

If the load current I _L of the logic circuit changes and changes from I ₀ to I ₁ , the voltage drop at Q ₁ will increase, so the value of V _DD will fall below V ₀ and reach the value of V ₁ . do. Therefore, the value of V _G becomes larger than the value of V _G0 in FIG. 4 and tends to reach the value of V _G1 .

Since _the gate voltage of Q ₁ increases, the current that can flow through Q ₁ increases, resulting in the characteristics shown in _{FIG .} Generated as a voltage. When the load current becomes smaller and becomes I ₂ , the initial voltage drop of Q ₁ becomes smaller, so the voltage at terminal 6 becomes a little higher, V ₂ ,
The voltage at the inverter output 7 decreases to a value of V _G2 .

In _other words, as the voltage of Q ₁ becomes lower, the current that can flow through _{Q 1} becomes smaller, resulting in the characteristics shown in _FIG . generated. In other words, an almost constant voltage is generated by changing the characteristics of the voltage drop transistor Q ₁ in response to a change in the load current through negative feedback.

FIG. 5 shows the characteristics of the voltage V _DD generated at the terminal 6 with respect to the load current I _L. A nearly constant voltage is generated for I _L until V _G equals the value of V _GG .

Also, considering the fluctuations in the externally supplied power supply voltage V _GG , if the load current I _L is I ₀ when the value of V _GG is V _{GG 0} , the generated voltage V _DD in Figures 6 and 7 is _V0 , and the gate voltage _VG of _Q1 is in an equilibrium state at _VG0 . If V _GG increases from V _GG0 to V _GG1 , the value of V _DD becomes higher than V ₀ .
It becomes V ₁ . Therefore, the gate voltage V _G of Q ₁ decreases from V _G0 to V _G1 , and the characteristics of Q ₁ change from 11 to 1 in FIG.
Changes to 2.

Therefore, the generated voltage V _DD becomes I ₀ on characteristic 12, V ₁
becomes the value of Also, when V _GG decreases to the value of V _GG2 , the voltage at terminal 6 becomes V ₂ , the gate voltage of Q ₁ increases to V _G2 , and the characteristics of Q ₁ become as shown in Figure 6.
3, and the value V ₂ of V _DD corresponding to I ₀ is generated.

In other words, in response to changes in the external power supply voltage, an almost constant voltage is generated by changing the characteristics of the voltage drop transistor _Q1 through negative feedback. FIG. 8 shows the characteristics of the generated voltage V _DD with respect to the externally supplied power supply voltage V _GG . If the value of V _GG is greater than or equal to the sum of the threshold voltages of enhancement type MOSFET _{Q 2} and Q ₄ , an almost constant voltage is generated.

Another embodiment of the present invention is a case where the voltage drop transistor _Q1 , which is the depletion type MOSFET explained in FIG. 2, is replaced with an enhancement type MOSFET, and the characteristics of _Q1 are as shown in FIG. 9. _Q1
As explained above when is a depletion type MOSFET, if the load current is large, Q ₁
Since the gate voltage of Q 1 becomes high, the characteristics shown in FIG. 9 will be obtained, and if the load current is small, the gate voltage of Q ₁ will decrease, resulting in the characteristics shown in FIG. 9, 16. Therefore, the voltage remains almost constant with respect to fluctuations in the load current, and the characteristics shown in FIG. 5 are obtained.

In addition, regarding fluctuations in the external power supply voltage, as shown in Figure 10, as the power supply voltage increases, the gate voltage decreases, resulting in the characteristics shown in Figure 10 (19), and as the power supply voltage decreases, the gate voltage increases. Figure 18
The characteristics shown in FIG. 8 are obtained, and the voltage remains almost constant against fluctuations in the power supply voltage, and the characteristics shown in FIG. 8 are obtained.

In this case _{, the} generated voltage _becomes constant because _the value of the power supply voltage _V This is because the voltage is higher than the sum of the hold voltages.

In the two specific examples mentioned above, Q ₃ , Q ₆ , and Q ₈ are depletion type MOSFETs, but Q ₃ , Q ₆ , and Q ₈
Even if the circuit shown in Fig. 11 is made by using enhancement type MOSFETs Q ₉ , Q ₁₁ , and Q ₁₃ , Q ₁₀ and
The inverters Q ₁₁ , Q ₁₂ and Q ₁₃ are driven by drive transistors Q ₁₀ and Q ₁₂ and load transistors Q ₁₁ and
The gm ratio of Q ₁₃ is made extremely large, so that the output changes greatly in response to slight changes in the gate voltage of Q ₂ . An almost constant voltage can be generated in the same way as described above.

In addition, in the circuit shown in Figure 2, when Q ₁ and Q ₃ are depletion type MOSFETs and _{Q 2} is an enhancement type MOSFET, the generated voltage with respect to the change in threshold voltage of the enhancement type MOSFET and depletion type MOSFET is as follows. Become. If the threshold voltage V _TE of the enhancement type MOSFET becomes large, the characteristic 20 shown in FIG.
As shown in , it moves in parallel to the right by twice the amount of change in V _TE , and the generated voltage V _DD increases by that amount. Furthermore, if V _TE is small, as shown at 22 in FIG. 12, there is a parallel shift to the left by twice the amount of change in V _TE , and the generated voltage becomes smaller by that amount. In other words, the generated voltage is
Proportional to 2V _TE +ΔV _TE .

Also, the change in the threshold voltage V _TD of the depletion type MOSFET, that is, the depletion type MOSFET
In response to changes in the current I _TD that can flow through the MOSFET, the inverter characteristics 23 shown in _FIG.
When becomes large, the inverter characteristics become as shown in 24. However, if all the load MOSFETs in the logic circuit section 4 are composed of depletion type MOSFETs, the load current I _L is proportional to I _TD , so I _TD
As the value increases, it changes from I ₀ to I ₈ .

The load current flowing through the logic circuit section is proportional to V _TD ² , but the current that can flow through Q ₁ is proportional to (V _G + V _TD ² ), so when V _TD increases, V _G must decrease, and therefore the The voltage V _DD increases as the value of V ₈ and is proportional to I _TD . Also, V _TD becomes smaller. In other words, as I _TD becomes smaller, V _G needs to become higher, and the value of V _DD becomes smaller like V ₉ and I _T
Proportional to _D. The minimum value of the clock level required for the clock generation section and clock oscillation section for the logic circuit section composed of E/D MOS to operate is
It is proportional to 2V _TE +ΔV _TE and also proportional to I _TD . Therefore, on the same chip, the constant voltage circuit of FIG. 2 in which Q ₁ and Q ₃ of the present invention are depletion MOSFETs and the E/
By configuring the logic circuit section with a DMOS configuration, it is possible to always supply a voltage slightly higher than the minimum clock level value _VLMIN required by the logic circuit section from the constant voltage circuit. Since excessive clock voltage does not enter the transfer gate of the logic circuit section, malfunctions due to capacitive coupling in the transfer gate are prevented. Additionally, in the past, there was a possibility that a voltage higher than the threshold voltage of the parasitic MOS in the field could be applied, so a channel stopper was installed in the field to increase the threshold voltage of the parasitic MOS to prevent parasitic MOS from forming. However, by operating the clock oscillator and clock generator from a constant voltage circuit that generates a voltage slightly higher than 2V _TE + ΔV _TE of the present invention, a constant voltage can be achieved even if manufactured using a process that does not include a channel stopper in the field section. Parasitic MOS does not occur because the voltage generated by the circuit is lower than the threshold voltage of parasitic MOS. Therefore, the step of creating a channel stopper can be omitted, reducing costs by reducing the number of steps, and eliminating the junction capacitance between the channel stopper and the wiring in the diffusion layer, resulting in a significant reduction in the capacitance of the wiring in the diffusion layer. , the switching speed is correspondingly faster, resulting in faster operation for the same power consumption. In addition, since channel stoppers can be eliminated, the wiring spacing in the diffusion layer can be narrowed, allowing high-density
Can manufacture LSI.

Also, since the speed is increased, in the case of E/D MOS LSI, the switching speed of the element is proportional to I _TD , but I _TD can be lowered by the increased speed, and power consumption can be reduced accordingly. Further I
When _{the TD} is lowered, the high power supply voltage _VGG generally required for clock power supplies can be lowered, further reducing power consumption. This means high speed and ultra-low power consumption.
It has the great advantage of being able to provide MOS LSI.

In addition, since the internal voltage is constant and low, it is possible to use elements with short channel lengths, and the wiring spacing due to the diffusion layer can also be narrowed, making it possible to achieve significantly higher density and thus reduce the chip size. We can provide low-cost LSI.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional example, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Fig. 3 is shown in Fig. 2.
The Q ₁ characteristic (load current change) diagram, Figure 4 shows the inverter characteristics of the three stages connected in series of Q ₂ Q ₃ Q ₄ , Q ₅ Q ₆ , Q ₇ Q ₈ shown in Figure 2, and Figure 5 shows the inverter characteristics of the three stages connected in series. A diagram showing the generated voltage with respect to the load current in an embodiment of the present invention, FIG. 6 is a diagram of the characteristics (power supply voltage change) of Q ₂ shown in FIG. 2, and FIG. 7 is a diagram showing the characteristics of Q ₂ and Q ₄ shown in FIG. 2. and Q ₃ , Q ₅ and Q ₆ , Q ₇ and
Characteristics of three stages of _Q8 inverters connected in series,
Figure 8 shows the generated voltage characteristics with respect to V _GG , Figure 9 shows the characteristics of Q ₂ shown in Figure 2, and Figure 10 shows the characteristics of Q 2 shown in Figure 2.
The characteristics of Q ₂ , Fig. 11 is a circuit diagram showing another embodiment of the present invention, and Fig. 12 shows the characteristics of Q ₂ with respect to V _TE changes.
Figure 13 shows _{the inverter} characteristics of three stages connected in series with _{Q 4} and Q _{3 ,} Q ₅ and Q _{6 ,} and Q ₇ and Q _{8 .} , Q ₇ and Q ₈ connected in series, and FIG. 14 shows the characteristics of Q ₁ with respect to V _TD changes. 1, 4...Logic circuit section serving as load, 2, 5...
External power supply terminal, 3, 6...Generation power supply terminal, 7...
Inverter output terminals for Q ₇ and Q ₈ .

Claims (1)

[Claims] 1 a first insulated gate field effect transistor connected between a power source and an output terminal; and a third insulated gate field effect transistor, one end of which is connected to the power source or another power source via a second insulated gate field effect transistor. a fourth insulated gate field effect transistor connected between the other end of the third transistor and a reference potential and having a gate connected to the other end of the third transistor; A signal having the same phase as a signal at the one end of the third transistor is applied to the gate of the first transistor, and the gate of the third transistor is connected to the output terminal. Constant voltage circuit.