JPS6240885A - Speed error correction circuit for time base correcting device - Google Patents

Abstract

PURPOSE:To improve the responsiveness of a time base corrector to a high-fre quency jitter by internally inserting the speed error of one field before to the speed error signal of the current field through a memory at a switching circuit and using the speed error signal thus obtained as a speed error signal. CONSTITUTION:From a speed error detecting circuit 11 the speed error signal S1 of the current field is obtained at every one horizontal period at, for instance, an impact error section. Moreover, the speed error signal S2 of one field before is obtained from a field memory 15 at, for example, the impact error section. A speed error signal S1' which is produced by internally inserting the signal S2 into the signal S1 is obtained from a switching circuit 14 at every 1/2 horizon tal period and supplied to a speed error memory 12. Since the detecting fre quency of speed errors is substantially doubled in such a way, the responsiveness of a time base corrector to a high-frequency jitter can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a speed error correction circuit for a time base correction device (TBC) used, for example, in a playback system of a video tape recorder (VTR).

[Summary of the invention]

The present invention substantially doubles the entire speed error detection frequency in the TBC speed error correction circuit.
This improves the response of TBC to high frequency jitter.

[Conventional technology]

FIG. 3 shows an example of a TBC used, for example, in a reproduction system of a VTR.

In the figure, a reproduced color video signal Sv from a VTR is supplied to a terminal (1). This video signal Sv is supplied to a sync separation circuit (2) and a burst separation circuit (3). The synchronization signal from the synchronization separation circuit (2) is AFC
A clock that follows the frequency of the video signal Sv is obtained from the AFC circuit (4), and this is supplied to the APC circuit (5). Also, this APC
The burst signal from the burst separation circuit (3) is supplied to the circuit (5). Then, this APC circuit (5) obtains a signal that follows the frequency of the video signal Sv and is phase-locked to the burst signal (for example, 4j'gcCf5a is the burst frequency), and this is used as the write clock. This write clock is supplied to the converter (6) and the memory (7).

Moreover, the video signal Sv supplied to the terminal (1) is A/D
After being converted into a digital signal by a converter (6), it is stored in a memory (7).
). Then, it is written and stored in this memory (7) using the above-mentioned write clock, and
The stored contents are read out using a read clock that has the same frequency as the write clock and is created taking all time axis fluctuations into account.

In addition, (8) is a read clock generator, and the read clock of a constant frequency (4fsc) is transmitted to the memory (7) and the D/A converter αO via the phase modulation circuit (9).
supplied to

In addition, the burst signal from the burst separation circuit (3) is supplied to the speed error detection circuit 0), a speed error is detected by this detection circuit α, and the speed error signal is supplied to the speed error memory (6). is memorized. and,
From this speed error memory 0◇, speed error signals corresponding to the video signals read out from the memory (7) are sequentially read out and supplied to the phase modulation circuit (9). The read clock supplied to the D/A converter α1 is phase modulated.

Therefore, a good video signal with the time i1 error corrected can be obtained at the output terminal α.

The details of the TBC as shown in Fig. 3 can be found, for example, in
It is described in No.-9319.

[Problem that the invention seeks to solve]

By the way, in the speed error correction circuit in the TBC shown in FIG. 3, the detection frequency of the speed error of speed error detection circuit
4 kHz), and from the sampling theorem it is impossible to detect more than one horizontal frequency.

Therefore, even if a speed error correction circuit is used, the TBC's response to time axis fluctuations is about 3 kHz, and the response to high frequency jitter is poor, resulting in residual errors.

In view of this point, the present invention improves the responsiveness to TBCO high frequency jitter.

[Means for solving problems]

The present invention is intended to effectively correct impact errors caused by so-called head striking, particularly in VTRs using rotating magnetic heads.

The present invention provides a memory having an Efield capacity (IFJ).
and a switch circuit 0 are provided, and the speed error signal S2 of one field before, which is passed through the memory 0, is interpolated into the speed error signal S of the current field by the switch circuit α◆.
This is the speed error signal S1/.

[Effect]

Impact errors due to so-called head striking occur at the same position from the vertical synchronization position in each field, and their frequency and level are approximately constant. Furthermore, due to interlacing, the horizontal synchronization position is shifted by 0.5 horizontal interval between the first field and the second field.

From the above, as described above, a new speed error signal 81 is obtained by interpolating the speed error signal S2 of one field before, which has been passed through the memory (I→), into the speed error signal S of the current field.
' is the detection frequency substantially doubled.

〔Example〕

The present invention focuses on the following points.

That is, in a VTR using a rotating magnetic head, there is an impact error caused by so-called head striking. This impact error occurs at a position equal to the vertical synchronization position in the name field, and its frequency level is approximately constant. Furthermore, due to interlacing, the horizontal synchronization position is shifted by 0.5 horizontal interval between the first field and the second field.

An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In the figure, the speed error signal S1 obtained from the speed error detection circuits α is directly supplied to the switch circuit 0, and is also supplied to the field memory 0→ which constitutes the field delay line. Then, the speed error signal S2 of the previous field from the field memory OQ is supplied to the switch circuit θ bar.

In this case, speed error +is1. s2 is detected every horizontal period (1H), and as mentioned above,
Since the horizontal synchronization position is shifted by 0.5 horizontal interval between the first field and the second field, the speed error detection L13 signals S1 and 82 are shifted by 0.5 horizontal interval.

The switch circuit 04 is switched to alternately take out the speed error detection signals S1 and 82.

Then, from this switch circuit (1Φ), a signal S' is obtained by interpolating the speed error detection signal S2 into the speed error detection signal S, and this signal 81' is used as the speed error signal and is stored in the speed error memory. α is supplied and stored.

The rest of the structure is the same as the example shown in FIG.

In this example, from the speed error detection circuit 0η, a speed error signal S of the current field is obtained every horizontal period (IH), as shown by the "○" mark in FIG. 2A, for example at a portion of the impact error. . Also, field memory α
From υ, for example, in a part of the impact error, the second
As shown by the symbol "△" in FIG. B, the speed error signal S2 of one field before is obtained every horizontal period. Then, from the switch circuit θ→, as shown in FIG. and is supplied to the speed error memory α→.

As described above, according to this example, the speed error detection frequency is substantially doubled (see FIG. 2C), so that the responsiveness of the TBC to high frequency jitter can be completely improved. This is particularly effective for correcting in/9 point errors caused by head striking.

In the above-described embodiment, speed error correction is performed not only in a portion of the impact error but also in all portions, but the correction may be made in only a portion of the impact error. In this case, for example, only in a part of the impact error, the switch circuit 0 → speed error memory 0
→ is supplied with a speed error signal S1'.

Also, by averaging the speed error signal 81' using memory, S/'N? It can be amplified.

[Effects of the Invention] According to the present invention described above, the speed error detection frequency is substantially doubled, so that the response to TBCO high-frequency jitter can be improved. The present invention is particularly effective for correcting impact errors caused by head striking.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining the same, and FIG. 3 is a block diagram showing an example of a TBC. αη is a speed error detection circuit, (6) is a speed error memory, α→ is a switch circuit, and α→ is a field memory.

Claims (1)

[Claims] A memory having a capacity of one field and a switch circuit are provided, and the switch circuit interpolates the speed error signal of one feed before the current field into the speed error signal of the current field, and this A speed error correction circuit for a time axis correction device, characterized in that the speed error signal is used as a speed error signal.