JPS6237100A - Controller for stepping motor - Google Patents

Abstract

PURPOSE:To control a slow-down and a speed-up minutely by applying driving pulses optimum to an actuating system to a stepping motor. CONSTITUTION:A CPU 1 prepares pulse patterns in response to the pulse informations of driving pulses to be inputted. A ROM 2 stores programs and data controlling each unit. A RAM 3 consists of a pulse pattern table memory storing the pulse patterns, and functions as a work memory. A timer 5 serves as a pulse generating means, and generates driving pulses 27 in response to the pulse patterns written to the pulse pattern table memory and drives a stepping motor 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a stepping motor control device that controls the driving of a stepping motor by varying the frequency of driving pulses applied to the stepping motor over time.

[Conventional technology]

When driving a stepping motor as an actuator, the pattern of driving pulses to be applied must be set according to the specifications of the system used.

The drive pulse pattern is determined by considering the following items.

(1) Due to its characteristics, a stepping motor cannot be started or stopped rapidly, and it is necessary to gradually increase (slow-up) or gradually decrease (slow-down) the frequency of drive pulses.

(2) Margin for system load fluctuations and environment.

(3) System resonance.

(4) Movement specifications (speed 2 hours 9 positions 9 rotation directions).

Therefore, in order to determine the optimal drive pulse pattern, a stepping motor control device that can variably set the drive pulse pattern is required.

[Problem that the invention seeks to solve]

However, conventionally, this type of device has adopted a trapezoidal drive or a triangular drive (a drive method in which the frequency of the drive pulse is linearly changed over time to achieve slow-up and slow-down), and has been used to drive a stepping motor (hereinafter referred to as "stepping motor"). Since the step motor (abbreviated as step motor) is controlled, the slope and length of the straight line can be varied, but there are various types of drive during slow-up and slow-down, such as the frequency of the drive pulse changing logarithmically over time. It is not possible to perform a drive in which the relationship between the frequency and time of the drive pulse is linear, and the range for determining the optimal drive pulse pattern for starting and stopping the step motor is limited.
There have been problems such as the inability to apply an optimal drive pulse to the step motor that matches the system to be actuated.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a stepping motor control device that can supply a stepping motor with drive pulses that are optimal for the system to be actuated.

[Means for solving problems]

A stepping motor control device according to the present invention includes: a pulse pattern creation means for creating a pulse pattern according to pulse information of a drive pulse inputted from an input means; a pulse pattern table memory for storing the pulse pattern; and a pulse pattern table memory for storing the pulse pattern. This device is provided with pulse generating means for generating drive pulses to drive the stepping motor in accordance with the pulse pattern written in the table memory.

[Effect]

In this invention, when the pulse pattern creation means creates a pulse pattern according to the pulse information of the drive pulse inputted from the input means, this pulse pattern is written into the pulse pattern table memory. The pulse generating means outputs drive pulses according to the pulse pattern written in the pulse pattern table memory.

〔Example〕

FIG. 1 is a block diagram illustrating a control device for a stepping motor according to an embodiment of the present invention, and 1 is a block diagram illustrating a control device for a stepping motor according to an embodiment of the present invention.
U controls each unit. Further, the CPUI constitutes a pulse pattern creation means of the present invention. 2 is ROM
It stores programs and data that control each unit.

3 is R forming the pulse pattern table memory of this invention.
AM functions as a working memory. 4 is a timer,
Used for display, key manual or internal time management. 5
is a timer which constitutes a pulse generating means of the present invention, and outputs a drive pulse 27, which will be described later. The timer 4.5 is composed of a single chip such as a programmable interval timer IC (8253 or 8254), for example. 6 is I10
The data bus 17 is connected to the outside using the boat. For example, a programmable peripheral interface IC (8255) is used for the port 6 of the device 10. 7.8 is a driver, and 9 is a step motor driver circuit, which outputs a drive signal 32 suitable for driving the step motor 10 in response to the drive pulse 27. 11 is an address decoder which responds to the signals of the address bus 18, ROM2, , R
AM3.

Timer 4. Timer 5. Select signals 22, 23, 24 and 25, 26 for selecting one of the I10 ports 6 are created. A crystal oscillator 12 generates a reference clock signal 16. 13 and 14 are edge trigger type flip-flops (hereinafter referred to as FF). Reference numeral 15 denotes a display/key manual input device through which key manual data is input via the driver 8, and output data is received and displayed. A clock signal (CLK) 19 is generated by frequency-dividing the reference clock signal 16. 20 is a read signal (RD), 21 is a write signal (WR), and 28 is an output pulse signal (OUTI), which are output from the timer 4.

29 is an output pulse signal (OUT2), which is output from the timer 5. Reference numeral 30 denotes motor information, which indicates information necessary for the step motor driver circuit 9 (step angle 9 rotation direction, current ON-OFF, countdown, etc.) and the state of the drive signal 32. A timer drive signal (GATE L) 33 controls starting and stopping of the timer 4. A timer drive signal (GATE2) 34 controls starting and stopping of the timer 5. A reset signal 35 resets the edge trigger type flip-flop 13. 36 is a reset signal,
The edge trigger type flip-flop 14 is reset.

37 is an interrupt signal, which is input to the interrupt terminal R3Tl of the CPU1. 38 is an interrupt signal, which is connected to the interrupt terminal R3T of CPU1.
2 is input.

According to a control program written in advance in the ROM 2, the CPU 1 transfers information input by the operator using the display/key manual device 15 to the driver 8. I10 port 6
It is stored in RAM 3 in a certain format via . In particular, display and
The key manual control is executed by applying an interrupt to the interrupt terminal R5Tl of the CPU 1 via the FF 13 in response to a constant cycle pulse signal generated by the timer 4.

Next, the CPU instructs the timer 5 to generate a predetermined drive pulse 27 in accordance with the information stored in the RAM 3.
Write data to. CPUI display/key human power device 1
A starting signal (MO
When receiving the H level 8) of the TOR ON signal, the RAM
Among the information stored in 3, the information necessary for the step motor driver circuit 9 (step angle 2 rotation direction, current 0N)
-OFF, countdown, etc.) is output as motor information 3o via the I10 boat 6, and further provided to the step motor driver circuit 9 via the driver 7. Thereafter, the CPUI sets the timer drive signal 34 to an H level state in order to output the drive pulse 27. The drive pulse 27 generated thereby is supplied to the step motor driver circuit 9 via the driver 7, and the step motor driver circuit 9 rotates the step motor 1o by one step angle every time an edge (falling edge) of the drive pulse 27 is detected. A current is applied as a drive signal 32 to each phase of the motor so that the motor rotates by the same amount. Further, the drive pulse 27 is sent to the FF 13 as an output pulse signal 29 via the driver 7, and the output pulse signal 2
The edge (falling edge) of 9 is detected and applied as an interrupt signal 37 to the interrupt terminal R5T1 of the CPU1. In this interrupt processing, whether or not a predetermined number of pulses have been output to the step motor driver circuit 9 is determined by counting the number of interrupts (the number of edges (falling number) of the output pulse signal 29).

When the CPU 1 finishes outputting a predetermined number of pulses, or receives a motor stop signal (MO
When receiving the L level state 8) of the TOR10N signal, the timer drive signal 34 is set to the L level state in order to stop the drive pulse 27 of the timer 5.

Next, the operation of the timer 5 will be explained with reference to FIGS. 2(a) to 2(d).

FIGS. 2(a) to 2(l) are time charts illustrating the operation of the timer 5. FIG.

In this figure, (a) shows the clock signal 19, and (
b) shows the timer drive signal 34, which enables counting when in the H level state and the drive pulse 27 when in the L level state.
is set to H level. (C) is the drive pulse 27 (
(d) shows the output pulse signal 29), and (d) shows the write signal 21.
In the L level state, the counter setting value n is written to the timer 5.

As can be seen from this figure, the drive pulse 27 becomes the L state when half of the counter setting value n is counted (however, if n is an odd number, when counting (n-1) 72 minutes), the driving pulse 27 reaches the counter setting value n is, for example, r6J to r4J
When the current count output changes to point A, the counter operates with a new counter setting value (n=4). Such operation is performed using a programmable interval timer IC (82
When using a one-chip timer 5 such as 53 or 8254), the mode may be set to "3". The mode is set by writing data to an internal register (not shown) of the timer 5. By changing the counter setting value in this way, the driving pulse 27. The frequency of the output pulse signal 29 can be varied.

Similarly, when the timer 4 is configured with a single chip such as a programmable φ interval timer IC (8253 or 8254), the mode is set to F3j. The output pulse signal 28 of the timer 4 is input to the interrupt terminal R5Tl of the CPU 1 via the FF 13. Since the interrupt here performs display and key manual processing, it is sufficient that the interrupt occurs at a fixed period, and this can be realized by once writing a constant in the timer 4 as a counter setting value.

Next, referring to FIGS. 3 and 4, the driving pulse 27 is
and a method of generating the output pulse signal 29 will be explained.

FIG. 3 is a diagram explaining the pulse information stored in the RAM 3, where X indicates the step number, fx indicates the frequency of the drive pulse 27 (output pulse signal 29) at step X, and Px indicates the frequency at step X. CX indicates the counter setting value of the counter 5 of the drive pulse 27 (output pulse signal 29) at step X, and Δtx indicates the time of step X. . Note that n is a finite integer determined from the capacity of the RAM 3. This information is stored as table data at a predetermined location on the RAM 5, and can be read out at any time.

Furthermore, the relationship between the frequency fx and the counter setting value CX is as follows: If the frequency of the clock signal 19 is fΦ, then Cx"fΦ/
fx, and CX is automatically calculated from fx. The drive pulse 27 is generated based on the stored information, particularly the number P8 of drive pulses 7.27, the counter setting value Cx, and the step X.

FIGS. 4(a) and 4(b) are time charts for explaining the slow-up pulse pattern of the drive pulse 27, and FIG.
), the same parts as in FIG. 3 are given the same reference numerals. In the same figure (b), the vertical axis indicates the frequency f×,
The horizontal axis indicates time Δt×.

To input the pulse pattern information of the drive pulse 27, basically, input the number of steps n, the frequency fx of the drive pulse at each step, and the drive pulse Px from the keyboard of the display/key human power device 15, and then input it on the RAMa. This is done by setting (abbreviated as format 1). The number of steps n at this time has a certain upper limit because there is a limit to the memory capacity. The lower limit is n=1.

Note that the counter setting value CX and the time Δt of step
8, CPU1 automatically executes the following section (1).

Calculate using formula (2).

Cx=fΦ/ f x (1) Δt
X = CX - Px (2) where fΦ is the frequency of the clock signal 19 and is set at the initial stage.

The pattern of the drive pulse 27 shown by the solid line in FIG. 4(b) is a pulse with an intermediate frequency when the period from fall to fall of the drive pulse 27 is measured to include connection points of pulses with different frequencies. This is a pulse pattern that can be considered as . This works to reduce the change in frequency over time when slowing up and slowing down.
Achieve smooth drive.

Note that when the drive signal 32 is triggered at the rising edge of the drive pulse 27, the drive pattern shown by the dotted line shown in FIG. 4(b) is obtained.

Next, while referring to FIGS. 5(a) and (b), drive pulse 2
The setting operation in step 7 will be explained.

FIGS. 5(a) and 5(b) are flowcharts illustrating a pulse information table setting operation showing an embodiment of the present invention. (1) to (10) and (11) to (14) indicate each step.

First, wait for the motor start signal, that is, the drive signal 32 to go to the H level state (1), and until the drive signal 32 is received, the key manual receiver is in the state B (the timer drive signal 34 is at the L level).
Level status 1 interrupt is enabled, timers 4 and 5
is in mode r3J state), and when the drive signal 32 becomes H level, working register CNT (used as an addition counter to count the number of output pulse signals 29) and working register X (used as an addition counter to count the number of steps being executed) (used as an addition counter) and flag register F
Clear LG to rOJ (2). Next, the counter setting value Co at the time of step is read from RAM3, and the timer 5
3), and by setting the timer drive signal 34 to H level (4), the timer 5 starts counting, and the drive pulse 27. at step 0 is set. The output pulse signal 29 is output. Drive pulse 27. When the output pulse signal 29 is output, the process proceeds to the interrupt routine shown in FIG. 5(b).
This occurs at every edge (falling edge in this case) of the output pulse signal 29. In interrupt processing, r is set in working register CNT.
11) and the output pulse signal 29
Count the number of pulses and check whether the working register CNT is equal to the number of pulses Po at step 0, that is,
The number of pulses Po at step 0 is actually the driving pulse 2.
7. It is determined whether the output pulse signal 29 has been output (12). If NO, the flow shown in FIG. 14), skips the interrupt processing and returns to the main routine processing shown in FIG. The drive pulse 27 and output pulse signal 29 are output at the frequency fO of the previously set value Co without writing a new one.When the flag FLG becomes rlJ, the flag FLG is cleared to rOJ6), and the working register ), if No, that is, if the value of working register X is smaller than the number of steps n, add 1j to working register
Set the counter setting value C1 for the next step 1 in the timer 58), and set the drive pulse 27.8 to have the next frequency f1. An output pulse signal 29 is output. This operation is performed so that the working register X becomes equal to the number of steps n, that is, all of the specified drive pulses 27. This process is repeated until the output pulse signal 29 is output.

On the other hand, if the determination in step (7) is YES, that is, if the working register Output pulse signal 2
9 is set to the H level state and the control is ended (10).

Next, the pattern information input operation of the drive pulse 27 according to the present invention will be described with reference to FIGS. 6 to 8.

FIG. 6 is a correlation diagram showing the relationship between the frequency of the drive pulse 27 and the number of output pulses, where the vertical axis shows the frequency fx and the horizontal axis shows the output pulse aPx. The following is the starting frequency F of the drive pulse 27.

The operation when slowing up (abbreviated as format 2) with the number of output pulses P from 1 to the stable frequency aF1 will be explained. In addition, the number of steps is n! is rloJ.

The input pulse information is the starting frequency F during slow-up.
o, number of pulses to output stable frequency Fio P+
, the number of steps nl.

The frequency fX of the drive pulse 27 of each step
), also in this case, the counter setting value Cx and the time Δtx of step X are determined by the above equations (1) and (2). Note that the relationship between frequency fx and time is not a straight line.

FIG. 7 is a correlation diagram showing the relationship between the frequency and time of the drive pulse 27, where the vertical axis shows the frequency f× (and the horizontal axis shows the time Δt× of step X. Hereinafter, the frequency f Data input of the drive pulse pattern when the drive pulse 27 is slowed down by the number of output pulses F from the starting frequency FO to the stable frequency F while maintaining a linear relationship between x and time Δ1x (abbreviated as format 3). The conversion operation will be explained.

The input pulse information is the starting frequency F during slow-up.
o, stable frequency F+, number of output pulses P+
, the number of steps is n+ (=8).

The relationship between the frequency fx of the driving pulse 27 of each step X, the number PX of output pulses, the time tX, and Δ - is given by the following equations (5) to (12).

fO=Fo ・・・・・・−
...(5) fX=α・Δtx−++fx−+(x=1~
n+) --([3) However, a = (F42-Fo
2)/(2・nl)...-(7)PX=P
] /rz (x=o”rz) ...-(8)
to=Q・・・・・・
(8) tX=tx-1+Δtx-+(x=1~n+)
”...(10)Δto=fΦ・Pa/fo
= (11) However, fΦ is the frequency Δtx of the clock signal 19 = tX + tx-1 (x = 1 to n
+) ・・・・・・(12) Of these, the (5th)
), Equation (8), Equation (9), and Equation (11), the frequency fo at step 770, the number of pulses Po, and the time t
o and Δto are calculated, and their values and equation (6),
From equations (8), (10), and (12), the frequency f1 at the next step 1, the number of pulses P+, and the time t
Find l and Δt1. This operation is repeated until step n], and frequency fX + number of pulses P is 9 hours tx
, Δt8 are determined. In this case, as shown in FIG. 7, the time tx and the frequency fx of the drive pulse 27 have a linear relationship, but the number of pulses Px and the frequency fx of the drive pulse 27 have a linear relationship as shown in FIG. is not a straight line.

FIG. 9 is a flowchart illustrating the information input operation of the drive pulse pattern according to the present invention.

Note that (21) to [31] indicate each step. Also,
The processing procedure of each step (21) to (31) is made into a subroutine and stored in the ROM 2 and RAM 3, so that it can be read out at any time.

First, the input format of the pulse pattern of the drive pulse 27 is selected (21), and information regarding the pulse pattern of the drive pulse 27 is input (22). Next, it is determined whether or not to change the input format (23), and if YES, the process returns to step (22); if NO, it is determined whether or not the pulse pattern information input has been completed (24), and if NO, step (22) is determined. ), and if YES, select the table creation method (25). Next.

Determine whether the input format and table creation method match (2B); if YES, proceed to step (28); if NO, determine whether to change the creation method (27); if YES, proceed to (25). Return, and if NO, return to step (21).

On the other hand, if the determination in step (26) is YES, create a table of the pulse pattern of the drive pulse 27.
8), then decide whether to convert the table or not.
9) In this judgment, if No, the control ends and returns to the main routine, if YES, it is decided whether to clear the table 30), and if YES, returns to (21),
If NO, specify the changes (31) and proceed to step (
Return to 25).

In the above embodiment, the case where the frequency f of the drive pulse 27 is changed is explained by detecting the edge of the drive pulse 27, but the time Δtx for outputting the same frequency fx may be calculated in advance. By managing the time using a newly installed counter, the frequency fx
It is possible to detect the point (time) at which the value changes.

In addition, in the above embodiment, if time information is input instead of the number of pulses, such as ΔtX that outputs the same frequency fx instead of the number of pulses Px in the information input method of the pulse pattern of the drive pulse 25, the rise time of the movement , fall time, etc., this is effective for finding a drive pulse pattern that matches the set time.

Furthermore, the input of the number P× of drive pulses 27 and the time period Δt
This may be done in combination with the input of ×.

〔Effect of the invention〕

As explained above, the present invention includes a pulse pattern creation means for creating a pulse pattern according to pulse information of a drive pulse inputted from an input means, a pulse pattern table memory for storing the pulse pattern, and a pulse pattern table memory for storing the pulse pattern. Since we have provided a pulse generation means that generates drive pulses to drive the stepping motor in accordance with the pulse pattern written in the Can be supplied to stepping motors,
It has the excellent advantage of being able to precisely control slowdown and slowup.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram illustrating a stepping motor control device showing one embodiment of the present invention, and FIG. 2(a) to
Cd) is a time chart explaining the operation of the timer, the third
The figures are diagrams explaining pulse information stored in the RAM shown in Figure 1, Figures 4 (a) and (b) are time charts explaining the slow-up pattern of drive pulses, and Figure 5 (a).
. (b) is a flowchart explaining the pulse information table setting operation showing an embodiment of the present invention; FIGS. 6 and 8 are correlation diagrams showing the relationship between the frequency of the drive pulse and the number of output pulses; FIG. 7 is a correlation diagram showing the relationship between drive pulse frequency and time, and FIG. 9 is a flowchart illustrating the information input operation of the drive pulse pattern according to the present invention. In the figure, 1 is the CPU, 2 is the ROM, 3 is the RAM, 4.5 is the timer, 6 is the I10 board, 7.8 is the driver, 9 is the step motor driver circuit, 10 is the step motor,]
1 is an address decoder, 12 is a crystal oscillator, 13.14
15 is an edge trigger type flip-flop, 15 is a display-key human input device, 16 is a reference clock signal, 17 is a data bus, ] 8 is an address bus, 19 is a clock signal, 20 is a read signal, 21 is a write signal, 22 to 26 is a select signal, 27 is a drive pulse, 28°29 is an output pulse signal, 30 is motor information, 32 is a drive signal, 33.34 is a timer drive signal, 35.36 is a reset signal, 37.38
is an interrupt signal. Fig. 6 1x Fig. 7 0 1 hour Δt8 Fig. 8 IKPX of 1 no χ tos

Claims (2)

[Claims] (1) A stepping motor control device that controls the driving of a stepping motor at a variable speed, comprising a pulse pattern creating means for creating a pulse pattern according to pulse information of a drive pulse inputted from an input means, and storing the pulse pattern. A stepping motor control device comprising: a pulse pattern table memory; and a pulse generating means for generating the drive pulses and driving the stepping motor according to the pulse pattern written in the pulse pattern table memory. (2) The stepping motor according to claim (1), wherein the pulse pattern creation means variably creates the frequency of the drive pulse and the number of drive pulses, and stores the created pulse pattern in a pulse pattern table memory. Control device.