JPH0876826A - Pulse generation circuit - Google Patents

Abstract

PURPOSE: To provide a pulse generation circuit which can cast change the frequency of a pulse signal into an optional pattern without using a storage means of a large capacity. CONSTITUTION: This pulse generation circuit includes the 1st and 2nd counters C1 and C2, a flip-flop FF, and the 1st and 2nd frequency dividers F1 and F2. The dividers F1 and F2 divide the clock signals CK in the given division ratios DR1 and DR2 and output the divided signals respectively. The counter C1 counts the pulses of the divided signal PL2 received from the divider F2 and applies a set signal S to the FF when the number of counted pulses reaches set value CT1. The counter C2 counts the pulses of the divided signal PL1 received from the divider F1 and applies a reset signal R to the FF when the number of counted pulses reaches set value CT2. The FF activates the dividers F1 and F2 when it is set and reset respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generator circuit for generating a pulse signal.

[0002]

2. Description of the Related Art In factory automation (FA), it is necessary to position a moving body with high accuracy. A positioning device that moves the moving body by a motor such as a stepping motor or a servo motor is used to position the moving body, and a positioning controller is used to control the positioning device.

The positioning controller uses a pulse generating circuit to generate a pulse signal corresponding to the moving speed and moving distance of the moving body, and supplies the pulse signal to the positioning device.
As a result, the motor moves the moving body at the moving speed corresponding to the frequency of the pulse signal by the moving distance corresponding to the number of pulses of the pulse signal.

Normally, when positioning a moving body,
As shown in FIG. 8, when the movement is started, the frequency of the pulse signal is gradually increased to gradually increase the speed of the moving body, and when the speed of the moving body reaches a predetermined speed, the frequency of the pulse signal is kept constant to move the moving body. The body is moved at a constant speed, and when stopped, the frequency of the pulse signal is gradually reduced to gradually reduce the speed of the moving body. Such control is called trapezoidal control.

In the conventional pulse generating circuit composed of hardware, the pulse signal can be changed only in a fixed pattern. Therefore, JP-A-56-661
Japanese Patent Publication No. 96 proposes an acceleration / deceleration circuit using a general-purpose timer. This acceleration / deceleration circuit stores the timer values corresponding to a plurality of frequencies in the memory, reads them sequentially and sets them in the timer, and changes the excitation phase of the motor by the time-up of the timer to perform the predetermined speed control. It is something to do.

[0006]

In the acceleration / deceleration circuit using the general-purpose timer described above, the speed control and the positioning can be performed in various acceleration / deceleration patterns by storing the timer values of various patterns in the memory. .

However, since the required memory capacity increases as the acceleration / deceleration pattern increases, there is a limit to the amount of the acceleration / deceleration pattern to be stored. Further, it takes some time to read the timer value from the memory and set it in the timer, so it takes time to switch the frequency. Therefore, although it can be used for a low speed stepping motor, it cannot be used for a high speed servo motor.

Furthermore, since the timer value corresponding to the acceleration / deceleration pattern must be stored in the memory in advance, the frequency of the pulse signal cannot be dynamically changed according to the frequency pattern calculated in real time.

An object of the present invention is to provide a pulse generation circuit which can change the frequency of a pulse signal at high speed and in an arbitrary pattern without using a large-capacity storage means.

[0010]

[Means for Solving the Problems]

(1) First Invention A pulse generating circuit according to the first invention is a first frequency dividing means,
A second frequency dividing means, a first counting means, a second counting means, an activating means and an output means are provided.

The first frequency dividing means divides the supplied clock signal into a set frequency division ratio and outputs the divided clock signal. The second frequency dividing means divides the supplied clock signal into a set frequency division ratio and outputs the divided clock signal. The first counting means receives the output signal of the second frequency dividing means, counts the number of pulses corresponding to the set count value, and outputs a count completion signal indicating completion of counting. The second counting means receives the output signal of the first frequency dividing means, counts the number of pulses corresponding to the set count value, and outputs a count completion signal indicating completion of counting. The activation means includes the first and second
In response to the count completion signal from the counting means of
And alternately activating the second frequency dividing means. The output means outputs the output signals of the first and second frequency dividing means as pulse signals.

(2) Second Invention A pulse generating circuit according to a second invention is a first storage means,
Second storage means, frequency dividing means and counting means are provided.

The first storage means stores the given count value. The second storage means stores the given frequency division ratio. The frequency dividing means divides the clock signal into a frequency division ratio given from the second storing means and outputs the divided frequency. The counting means receives the output signal of the frequency dividing means, counts the number of pulses corresponding to the count value given from the first storing means, and outputs a count completion signal indicating completion of counting.

The counting means fetches the count value from the first storage means in response to the count completion signal, and the frequency dividing means responds to the count completion signal from the counting means from the second storage means. Take in.

[0015]

[Action]

(1) First Invention In the pulse generating circuit according to the first invention, when the activating means is activating the first frequency dividing means, the first frequency dividing means sets the clock signal. The second counting means counts the number of pulses of the output signal of the first frequency dividing means. When the number of counted pulses reaches the set count value, the count completion signal is output. The activating means activates the second frequency dividing means in place of the first frequency dividing means in response to the count completion signal from the second counting means.

As a result, the second frequency dividing means divides and outputs the clock signal at the set frequency dividing ratio, and the first counting means counts the number of pulses of the output signal of the second frequency dividing means. To do. When the number of counted pulses reaches the set count value, the count completion signal is output. The activating means activates the first frequency dividing means in place of the second frequency dividing means in response to the count completion signal from the first counting means.

In this way, the first and second frequency dividing means are alternately activated, and the output signals of the first and second frequency dividing means are output as pulse signals by the output means.
In this case, the operating period of the first frequency dividing unit is determined by the count value set in the second counting unit, and the operating period of the first frequency dividing unit is determined by the frequency dividing ratio set in the first frequency dividing unit. The frequency of the pulse signal at is determined. The operating period of the second frequency dividing unit is determined by the count value set in the first counting unit, and the operating period of the second frequency dividing unit in the operating period is set by the frequency dividing ratio set in the second frequency dividing unit. The frequency of the pulse signal is determined.

Therefore, the frequency pattern of the pulse signal is set by setting an arbitrary frequency division ratio in each of the first and second frequency dividing means and setting an arbitrary count value in each of the first and second counting means. Can be set arbitrarily.

Further, while the first frequency dividing means and the second counting means are operating, the frequency dividing ratio and the count value are set in the second frequency dividing means and the first counting means, respectively. When the second frequency dividing means and the first counting means are operating, the frequency dividing ratio and the count value can be set in the first frequency dividing means and the second counting means, respectively. Thereby, the frequency division ratio and the count value can be switched at high speed.

Therefore, the frequency of the pulse signal can be changed at high speed and arbitrarily, and the frequency division ratio and the count value can be calculated in real time without storing all the frequency division ratios and the count values in the frequency pattern in advance. The frequency of the pulse signal can be dynamically changed by setting while calculating.

(2) Second Invention In the pulse generating circuit according to the second invention, the frequency dividing means divides and outputs the clock signal to the frequency dividing ratio given from the second storing means, and the counting means. Counts the number of pulses of the output signal output from the frequency dividing means. When the counted number of pulses reaches the count value given from the first storage means, the count completion signal is output. The frequency dividing means fetches a new frequency dividing ratio from the second storage means in response to the count completion signal, and the counting means fetches a new count value from the second storage means in response to the count completion signal. The output signal of the frequency dividing means is output as a pulse signal.

In this case, the operation period of the frequency dividing means is determined by the count value given to the counting means from the first storing means, and the frequency of the pulse signal is determined by the dividing ratio given to the frequency dividing means from the second storing means. Determined.

Therefore, by setting an arbitrary count value in the first storage means and an arbitrary frequency division ratio in the second storage means, the frequency pattern of the pulse signal can be set arbitrarily.

Further, while the counting means and the frequency dividing means are operating, the next count value and the next dividing ratio are set in the first and second storing means, respectively, so that the count value and the frequency dividing The ratio can be switched at high speed.

Therefore, the frequency of the pulse signal can be changed at high speed and arbitrarily, and the count value and the division ratio can be calculated in real time without storing all the count values and the division ratio in the frequency pattern in advance. The frequency of the pulse signal can be dynamically changed by setting while calculating.

[0026]

1 is a circuit diagram showing the configuration of a pulse generating circuit according to a first embodiment of the present invention. In FIG. 1, the pulse generation circuit 1 includes a first counter C1, a second counter C2, a flip-flop FF, a first frequency divider F1, and a second frequency divider F1.
Of frequency divider F2 and gate circuit G1.

A CPU (central processing unit) 21 sets count values CT1 and CT2 to the first counter C1 and the second counter C2, respectively. The first frequency divider F1 and the second frequency divider F2 have a CPU2
The frequency division ratios DR1 and DR2 are set by 1 respectively.
The CPU 21 receives the reference clock signal CK0 and gives the clock signal CK to the first and second frequency dividers F1 and F2.

The first frequency divider F1 divides the clock signal CK into a set frequency division ratio DR1 and outputs a frequency division signal PL1. The second frequency divider F2 divides the clock signal CK into a set frequency division ratio DR2 and outputs a frequency division signal PL2. The first counter C1 counts the number of pulses of the frequency-divided signal PL2 output from the second frequency divider F2, and outputs a count completion signal when the counted number of pulses becomes equal to the set count value CT1. Second counter C
2 is the frequency-divided signal PL1 output from the first frequency divider F1.
The number of pulses is counted, and when the counted number of pulses becomes equal to the set count value CT2, the count completion signal is output. The count completion signal output from the first counter C1 is used as the set signal S in the flip-flop F.
The count completion signal applied to F and output from the second counter C2 is applied to the flip-flop FF as the reset signal R.

When the set signal S is applied, the flip-flop FF activates the non-inverted output signal Q (for example, high level) and deactivates the inverted output signal / Q (for example, low level). The non-inverted output signal Q of the flip-flop FF is given to the first frequency divider F1 as an activation signal, and the inverted output signal / Q is given to the second frequency divider F2 as an activation signal. The frequency-divided signal PL1 output from the first frequency divider F1 and the frequency-divided signal PL2 output from the second frequency divider F2 are applied to the gate circuit G1, and the pulse signal PL is output from the gate circuit G1. To be done.

Next, the operation of the pulse generating circuit 1 of FIG. 1 will be described with reference to the timing chart of FIG. At time t1, when the set signal (count completion signal) S output from the first counter C1 rises to high level, the flip-flop FF is set, the normal output signal Q becomes high level, and the inverted output signal / Q Becomes low level. As a result, the first frequency divider F1 is activated and the second frequency divider F2 is deactivated. The first frequency divider F1 divides the clock signal CK into a frequency division ratio DR1 preset by the CPU 21 and outputs it as a frequency division signal PL1. The frequency-divided signal PL1 is output as the pulse signal PL via the gate circuit G1. Second counter C2
Counts the number of pulses of the divided signal PL output from the first frequency divider F1. During this time, the CPU 21 sets the next count value CT1 and the next frequency division ratio DR2 in the first counter C1 and the second frequency divider F2, respectively.

At time t2, when the number of pulses counted by the second counter C2 reaches the count value CT2 preset by the CPU 21, the reset signal (count completion signal) R rises to a high level. As a result, the flip-flop FF is reset, the normal output signal Q becomes low level, and the inverted output signal / Q becomes high level. As a result, the first frequency divider F1 is deactivated and the second frequency divider F2 is activated. The second frequency divider F2 divides the clock signal CK into a frequency division ratio DR2 set by the CPU 21 and outputs it as a frequency division signal PL2. This frequency-divided signal PL2 is output as a pulse signal PL via the gate circuit G1. First counter C1
Counts the number of pulses of the divided signal PL2 output from the second frequency divider F2. During this time, the second counter C2
The CPU 21 sets the next count value CT2 and the next frequency division ratio DR1 in the first frequency divider F1.

At time t3, when the number of pulses counted by the first counter C1 reaches the count value CT1 set by the CPU 21, the set signal (count completion signal) S rises to a high level. As a result, the flip-flop FF is set, the normal output signal Q becomes high level, and the inverted output signal / Q becomes low level. As a result, the first frequency divider F1 is activated and the second frequency divider F2 is deactivated.

In this way, the first frequency divider F1 and the second frequency divider F2 are alternately activated, and the first frequency divider F is activated.
1 and the frequency-divided signal PL1 and the second frequency divider F
The frequency-divided signal PL2 output from 2 is alternately output as the pulse signal PL via the gate circuit G1.

In this case, the frequency of the frequency division signal PL1 output from the first frequency divider F1 is determined by the frequency division ratio DR1 set by the CPU 21, and the number of pulses of the frequency division signal PL1 is set by the CPU 21 to the second frequency. It is determined by the count value CT2 set in the counter C2. Also, the second
The frequency of the frequency division signal PL2 output from the frequency divider F2 is determined by the frequency division ratio DR2 set by the CPU 21, and the pulse number of the frequency division signal PL2 is the count set by the CPU 21 in the first counter C1. It is determined by the value CT1.

Therefore, the first and second frequency dividers F
1 and F2 are set to arbitrary division ratios DR1 and DR2, respectively, and first and second counters C1 and C2 are set to arbitrary count values CT1 and CT2, respectively.
The frequency pattern of the pulse signal PL can be set arbitrarily.

When the first frequency divider F1 and the second counter C2 are operating, the frequency division ratio DR2 and the count value CT1 are respectively supplied to the second frequency divider F2 and the first counter C1. Set the second frequency divider F2 and the first
Of the first frequency divider F when the counter C1 of the
The frequency division ratio DR1 and the count value CT2 can be set in the first and second counters C2, respectively. Thereby, the frequency of the pulse signal PL can be switched at high speed.

For example, if the frequency of the clock signal CK is expressed by
When the frequency is 0 MHz, the frequency of the pulse signal PL is several Hz
It can be changed in the range of up to several MHz. further,
According to the frequency pattern calculated in real time by the CPU 21, the count values CT1, CT2 and the division ratio D
R1 and DR2 can be sequentially set in the first and second counters C1 and C2 and the first and second frequency dividers F1 and F2. Therefore, the frequency of the pulse signal PL can be dynamically changed without storing all count values and frequency division ratios in the frequency pattern in advance.

Further, in the pulse generation circuit 1 of the first embodiment, the frequency division signal P output from the first frequency divider F1.
By counting the number of L pulses by the second counter C2, switching from the first frequency divider F1 to the second frequency divider F2 is performed, and the pulse signal PL2 output from the second frequency divider F2. Since the switching from the second frequency divider F2 to the first frequency divider F1 is performed by counting the number of pulses of the pulse by the first counter C1, the duty of the pulse signal PL is accurately determined at the time of frequency switching. It is possible to reduce to 50%.

The duty of the pulse signal is always 50.
Becoming a% is important in positioning systems. FIG. 3 is a circuit diagram showing the configuration of the pulse generating circuit according to the second embodiment of the present invention. The pulse generation circuit 1 of FIG.
Buffer B1, second buffer B2, counter C3 and frequency divider F3.

The first buffer B1 temporarily stores the count value CT given from the CPU 21, and the counter C
Give to 3. The second buffer B2 temporarily stores the frequency division ratio DR given from the CPU 21, and gives it to the frequency divider F3. The CPU 21 receives the reference clock signal CK0,
The clock signal CK is given to the frequency divider F3.

The frequency divider F3 divides the clock signal CK into the frequency division ratio DR given from the second buffer B2, and outputs the divided signal as a pulse signal PL. The counter C3 counts the number of pulses of the pulse signal PL output from the frequency divider F3, and outputs the count completion signal CU when the number of counted pulses becomes equal to the count value CT given from the first buffer B1. , The next count value CT is fetched from the first buffer B1. The frequency divider F3 responds to the count completion signal CU output from the counter C3 and outputs the next frequency division ratio DR from the second buffer B2.
Take in. The CPU 21 responds to the count completion signal CU output from the counter C3 and outputs a new count value C.
T and a new frequency division ratio DR are calculated and given to the first and second buffers B2, respectively.

Next, the operation of the pulse generating circuit 1 of FIG. 3 will be described with reference to the timing chart of FIG. At time t11, when the count completion signal CU output from the counter C3 rises to a high level, the counter C
3 is the count value CT given from the first buffer B1
And the frequency divider F3 latches the frequency division ratio DR provided from the second buffer B2. The frequency divider F3 divides the clock signal CK into the latched frequency division ratio DR, and outputs the divided signal as a pulse signal PL. Counter C3
Counts the number of pulses of the pulse signal PL output from the frequency divider F3. During this period, the CPU 21 calculates the next count value CT and the next frequency division ratio DR, and sets them in the first buffer B1 and the second buffer B2, respectively.

At time t12, the count value CT in which the number of pulses counted by the counter C3 is latched
When it reaches, the count completion signal CU rises to a high level. As a result, the counter C3 has the first buffer B
The next count value CT given from 1 is latched, and the frequency divider F3 latches the next frequency division ratio DR given from the second buffer B2. The frequency divider F3 divides the clock signal CK into the latched frequency division ratio DR, and outputs the divided signal as a pulse signal PL. The counter C3 has a frequency divider F3.
The number of pulses of the pulse signal PL output from is counted. During this time, the CPU 21 calculates the next count value CT and the next frequency division ratio DR, and sets them in the first buffer B1 and the second buffer B2, respectively.

At time t13, the count value CT in which the number of pulses counted by the counter C3 is latched
When it reaches, the count completion signal CU rises to a high level.

In this way, the counter C3 performs the count operation based on the count value CT sequentially set in the first buffer B1, and the frequency divider F3 is operated by the frequency divider F3.
The frequency of the pulse signal PL changes by performing the frequency division operation based on the frequency division ratio DR that is sequentially set to.

In this case, the frequency of the pulse signal PL output from the frequency divider F3 is determined by the frequency division ratio DR given from the second buffer B2, and the number of pulses of the pulse signal PL is the first buffer. It is determined by the count value CT given to the counter C3 from B1.

Therefore, the frequency pattern of the pulse signal PL is arbitrarily set by setting the arbitrary count value CT in the first buffer B1 and the arbitrary frequency division ratio DR in the second buffer B2. You can

When the counter C3 and the frequency divider F3 are operating, the CPU 21 sets the next count value CT and the next frequency division ratio DR in the first and second buffers B1 and B2, respectively. Therefore, the frequency of the pulse signal PL can be switched at high speed.

Further, the count value CT and the frequency division ratio DR can be sequentially set in the first and second buffers B1 and B2 according to the frequency pattern calculated in real time by the CPU 21. Therefore, the pulse signal PL can be dynamically changed without previously storing all frequency division ratios and count values in the frequency pattern.

FIG. 5 is a diagram showing the configuration of a positioning system in which the pulse generating circuit 1 of the first and second embodiments is used. The positioning system of FIG.
0, a positioning controller 20 and a motor driver 30.

In the positioning device 10, the ball screw 12 is rotated by the rotation of the stepping motor 11. As a result, the moving body 13 fitted in the ball screw 12 moves in the direction indicated by the arrow X along the guide 14. At a predetermined position within the moving range of the moving body 13, the sensor 1 for stopping
5 are arranged. The sensor 15 is turned on when detecting the moving body 13 and generates a detection signal DET.

The positioning controller 20 includes a CPU 21 and a pulse generation circuit 22. The CPU 21 provides the pulse generation circuit 22 with various set values such as a count value and a frequency division ratio, and a clock signal. The pulse generation circuit 22 is the CPU 2
A pulse signal C for rotating the stepping motor 11 clockwise based on various set values given from 1.
W or a pulse signal CCW for rotating the stepping motor 11 in the counterclockwise direction is generated and given to the motor driver 30. The motor driver 30 drives the stepping motor 11 in response to the pulse signals CW and CCW from the pulse generation circuit 22.

First or second pulse generator 22
The pulse generation circuit 1 of the above embodiment can be used. However, a pulse signal C for rotating the stepping motor 11 clockwise as in the pulse generation circuit 22 of FIG.
When pulse signals CCW for rotating W and the stepping motor 11 counterclockwise are separately generated, two pulse generation circuits 1 are used. Alternatively, one pulse generating circuit 1 generates a pulse signal for controlling the rotation speed of the stepping motor 11, and
A direction output signal may be generated to control the rotation direction of the stepping motor 11.

By using the pulse generating circuit 1 of FIG. 1 as the pulse generating circuit 22, the moving body 13 can be moved in an arbitrary speed pattern. Thereby,
In addition to the trapezoidal control shown in FIG. 8, three-step trapezoidal control as shown in FIG. 6A and multi-step trapezoidal control as shown in FIG. 6B are possible.

Further, the speed of the moving body 13 can be dynamically changed while the CPU 21 calculates the frequency pattern. For example, as shown in FIG.
The frequency and the number of pulses from when the switch 5 is turned on to when it is stopped can be arbitrarily controlled. That is, since the frequency and the number of pulses of the pulse signal generated by the pulse generation circuit 1 are managed by the CPU 21, it is possible to arbitrarily perform control to stop at a predetermined number of pulses after the detection signal DET is input from the sensor 15. Is possible. Further, as shown in (b) and (c) of FIG. 7, it is possible to dynamically change the subsequent frequency pattern according to the timing when the sensor 15 is turned on.

Further, it is possible to control the frequency in an infinite operation loop while calculating the frequency pattern in real time. It is also possible to configure a part of the circuit forming the pulse generating circuit 1 by using the circuit in the CPU 21. Further, the first and second counters C1 and C2 and the flip-flop FF in the first embodiment may be replaced with a buffer, a counter and a switching means.

[0057]

According to the first and second aspects of the present invention, the frequency of the pulse signal can be changed at high speed in an arbitrary pattern, and the frequency pattern can be calculated without storing the frequency pattern in advance. It is possible to change the frequency dynamically.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a pulse generation circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the pulse generation circuit of FIG.

FIG. 3 is a circuit diagram showing a configuration of a pulse signal generation circuit according to a second embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the pulse generation circuit of FIG.

FIG. 5 is a diagram showing an example of a configuration of a positioning system in which the pulse generation circuits of FIGS. 1 and 2 are used.

FIG. 6 is a diagram showing an example of a frequency pattern that can be generated by the pulse generation circuit of FIGS. 1 and 2.

FIG. 7 is a diagram showing an example of a frequency pattern that can be generated by the pulse generation circuits of FIGS. 1 and 2.

FIG. 8 is a diagram showing a frequency pattern in trapezoidal control.

[Explanation of symbols]

 1 pulse generation circuit 21 CPU C1 first counter C2 second counter C3 counter F1 first frequency divider F2 second frequency divider F3 frequency divider FF flip-flop G1 gate circuit B1 first buffer B2 second The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (2)

[Claims] 1. A first frequency dividing means for dividing and outputting a given clock signal at a set frequency division ratio, and a given clock signal for dividing and outputting the given clock signal at a set frequency division ratio. A second frequency dividing means, and a first count which receives the output signal of the second frequency dividing means, counts the number of pulses corresponding to the set count value, and outputs a count completion signal indicating completion of counting. Means for receiving an output signal of the first frequency dividing means, counting the number of pulses corresponding to a set count value, and outputting a count completion signal indicating completion of counting; And activation means for alternately activating the first and second frequency dividing means in response to the count completion signal from the second counting means, and output signals of the first and second frequency dividing means. Is output as a pulse signal Pulse generating circuit and output means. 2. A first storage means for storing a given count value, a second storage means for storing a given frequency division ratio, and a frequency division for giving a clock signal from the second storage means. A frequency dividing means for dividing and outputting to a ratio, and a count completion signal for receiving the output signal of the frequency dividing means, counting the number of pulses corresponding to the count value given from the first storing means, and indicating completion of counting. And counting means for outputting a count value from the first storage means in response to the count completion signal, and the frequency division means for receiving the count completion signal from the count means. In response, the pulse generation circuit is characterized by taking in the frequency division ratio from the second storage means.