JPS6236808A - Manufacture of semiconductor hetero junction - Google Patents
Manufacture of semiconductor hetero junctionInfo
- Publication number
- JPS6236808A JPS6236808A JP17643285A JP17643285A JPS6236808A JP S6236808 A JPS6236808 A JP S6236808A JP 17643285 A JP17643285 A JP 17643285A JP 17643285 A JP17643285 A JP 17643285A JP S6236808 A JPS6236808 A JP S6236808A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- layer
- thin
- thickness
- thin layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【発明の詳細な説明】
〔概要〕
格子定数を異にする2種の半導体(第1の半導体と第2
の半導体)よりなり格子整合された半導体ヘテロ接合体
の製造方法である。[Detailed Description of the Invention] [Summary] Two types of semiconductors having different lattice constants (a first semiconductor and a second semiconductor) have different lattice constants.
This is a method for manufacturing a lattice-matched semiconductor heterojunction consisting of a semiconductor of
第1の半導体の層と第2の半導体の層との間に、第2の
半導体の厚さ数十人程度の薄層と第1の半導体の厚さ数
十人程度の薄層との組を少なくとも1組入れることとし
、この半導体薄層の組の格子定数を、第1の半導体に近
接する側から第2の半導体に近接する側に向って次第に
変化させて行き、この半導体薄層の組の格子定数を、第
1の半導体の格子定数から第2の半導体の格子定数に接
近させて行くものである。Between the first semiconductor layer and the second semiconductor layer, a combination of a thin layer of the second semiconductor with a thickness of about several tens of nanometers and a thin layer of the first semiconductor with a thickness of about several tens of nanometers is provided. The lattice constant of this set of semiconductor thin layers is gradually changed from the side close to the first semiconductor to the side close to the second semiconductor, and the lattice constant of this set of semiconductor thin layers is The lattice constant of the first semiconductor is made to approach the lattice constant of the second semiconductor from the lattice constant of the first semiconductor.
本発明は、半導体ヘテロ接合体の製造方法に関する。特
に、格子定数を異にする2種の半導体よりなり格子整合
された半導体ヘテロ接合体の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor heterojunction. In particular, the present invention relates to a method for manufacturing a lattice-matched semiconductor heterojunction made of two types of semiconductors having different lattice constants.
格子定数を異にする2種の半導体を使用して、半導体ヘ
テロ接合体を形成するには、従来、当該2種の半導体の
格子定数の中間の格子定数を有する八ツファ一層を介在
させていた。このような目的に使用されるバッファ一層
は、当該2種の半導体の一方または双方が化合物半導体
であるときはその混晶比を変更することにより得られる
ことが多いが、すべての半導体の組に対して、その中間
の格子定数を有する半導体(バッファ一層として好適な
半導体)が存在するとは限らないことは明らかである。Conventionally, in order to form a semiconductor heterojunction using two types of semiconductors with different lattice constants, a single layer of eight fibers having a lattice constant between the lattice constants of the two types of semiconductors was interposed. . A buffer layer used for such purposes is often obtained by changing the mixed crystal ratio when one or both of the two types of semiconductors are compound semiconductors, but it is On the other hand, it is clear that a semiconductor having a lattice constant in between (a semiconductor suitable as a buffer layer) does not necessarily exist.
八ツファ一層として好適な半導体が得られないときは、
格子不整合のま\ヘテロ接合体を製造せざるを得ない。When a suitable semiconductor cannot be obtained as a single layer of eight layers,
There is no choice but to manufacture a heterozygote with lattice mismatch.
このような場合でも、上層の半導体を十分厚く形成すれ
ば格子不整合そのものは治癒するが、格子不整合界面に
発生した結晶欠陥はそのま一成長することが一般である
ため、一般には層厚を厚くしても消滅するとは限らない
。そのため、格子定数を異にする2種の半導体を使用す
る場合、格子整合され結晶欠陥の存在しない半導体ヘテ
ロ接合体を製造することは容易ではなく、格子定数を異
にする2種の半導体よりなり結晶欠陥の存在しない半導
体ヘテロ接合体を製造する方法の開発が望まれていた。Even in such cases, if the upper layer semiconductor is formed sufficiently thick, the lattice mismatch itself can be cured, but crystal defects that occur at the lattice mismatch interface tend to continue to grow, so generally the layer thickness is Even if you make it thicker, it does not necessarily disappear. Therefore, when using two types of semiconductors with different lattice constants, it is not easy to manufacture a semiconductor heterozygote that is lattice matched and free of crystal defects. It has been desired to develop a method for manufacturing a semiconductor heterojunction free of crystal defects.
本発明の目的はこの要請に応えることにあり、格子定数
を異にする2種の半導体よりなり格子整合され結晶欠陥
の存在しない半導体ヘテロ接合体を製造する方法を提供
することにある。An object of the present invention is to meet this demand, and to provide a method for manufacturing a semiconductor heterojunction that is lattice-matched and free of crystal defects and is made of two types of semiconductors having different lattice constants.
上記の目的を達成するために本発明が採った手段は、格
子定数を異にする二つの半導体(第1の半導体と第2の
半導体)のヘテロ接合体を製造する場合、第1図に示す
ように、
イ、上記二つの半導体の層l、2の間に、第2の半導体
の厚さ数十A程度の薄層32と第1の半導体の厚さ数十
人程度の薄層31との組3を少なくとも1組入れること
とし、
口、この組をなす薄層32.31の層厚は、第1の半導
体の薄層31については、第1の半導体の層1から第2
の半導体の層2に向って次第に小さく、第2の半導体の
薄層32については、第1の半導体の層lから第2の半
導体の層2に向って次第に大きくすることにある。The means taken by the present invention to achieve the above object are as shown in FIG. So, a. Between the two semiconductor layers 1 and 2, there is a thin layer 32 of the second semiconductor with a thickness of about several tens of amps, and a thin layer 31 of the first semiconductor with a thickness of about several tens of amps. At least one set 3 is included, and the thickness of the thin layers 32 and 31 forming this set is the same as that for the first semiconductor thin layer 31 from the first semiconductor layer 1 to the second semiconductor layer 31.
The thickness of the second semiconductor thin layer 32 is gradually increased from the first semiconductor layer 1 to the second semiconductor layer 2.
格子定数がそれぞれa 、aBである2種の結品性物質
の薄膜4.5を第2図に示すように接触して形成すると
、これらの薄膜4.5の格子定数はいずれも、下式に示
すように、当該2種の結晶性物質の格子定数a 、a
の中間の値a。に変B
化することが知られている。When thin films 4.5 of two types of condensing substances with lattice constants a and aB are formed in contact as shown in Fig. 2, the lattice constants of these thin films 4.5 are both expressed by the following formula: As shown in , the lattice constants a and a of the two types of crystalline substances are
The intermediate value a. It is known to change to B.
但し、 fは格子不整合度であり、 d 、dBは、それぞれの結晶性物質 ^ の膜厚であり、 G 、G8は、それぞれの結晶性物質 のせん新車である。however, f is the lattice mismatch degree, d , dB are the respective crystalline substances ^ The film thickness is G, G8 are respective crystalline substances It is a new car.
本発明は、この性質を利用したものであり、第1図に示
すように、第1の半導体の層lと第2の半導体の層2と
の間に、第2の半導体の厚さ数十式程度の薄層32と第
1の半導体の厚さ数十人程度の薄層31との組3を少な
くとも1組入れることとし、この半導体薄層の組3の格
子定数を、第1の半導体lに近接する側から第2の半導
体2に近接する側に向って次第に変化させて行くことと
したものである。The present invention takes advantage of this property, and as shown in FIG. At least one set 3 of a thin layer 32 of approximately the thickness of the first semiconductor and a thin layer 31 of the first semiconductor having a thickness of several tens of layers is included, and the lattice constant of the set 3 of the semiconductor thin layers is set to be the same as that of the first semiconductor l. It is designed to gradually change from the side closer to the second semiconductor 2 to the side closer to the second semiconductor 2.
以下、図面を参照しつ覧、本発明の一実施例に係る半導
体ヘテロ接合体の製造方法についてさらに説明する。Hereinafter, a method for manufacturing a semiconductor heterojunction according to an embodiment of the present invention will be further described with reference to the drawings.
第3図参照
PbTe基板−LにP b T e o 、 s e
S e o 、 04層を形成する場合について述べる
。Refer to Fig. 3 PbTe substrate-L with P b T e o , s e
The case of forming the Seo, 04 layer will be described.
PbTeの格子定数は6.46人であり、P b T
e o 、 9e S e o 、 o i。The lattice constant of PbTe is 6.46, and P b T
e o, 9e S e o, o i.
の格子定数は8.448人であり、これらを直接接触さ
せた場合は格子整合しえない。そこで、PbTe基板1
とPbTeSe層2どの間に、PbTe層31とPbT
eSe層32との組を5組(PbTe基板lに近い方か
ら順に3a、3b、3c、3d、3e)設けることとし
、各層の厚さを下表の如くした。The lattice constant of is 8.448, and lattice matching cannot be achieved if these are brought into direct contact. Therefore, PbTe substrate 1
and PbTeSe layer 2, between PbTe layer 31 and PbT
Five sets (3a, 3b, 3c, 3d, 3e in order from the one closest to the PbTe substrate 1) with the eSe layer 32 were provided, and the thickness of each layer was as shown in the table below.
3 a 20 803 b
40 803 c 50
503 d 130
403 e 80 20成長方法
は通常のHWE法を使用した。3 a 20 803 b
40 803 c 50
503 d 130
403e8020 was grown using the normal HWE method.
以北のようにして製造したPbTe −PbTeSeヘ
テロ接合体を、 2,000倍の光学顕微鏡を使用して
観察したところ、異常成長部は全く観察されなかつた。When the PbTe-PbTeSe heterozygote produced as described above was observed using an optical microscope with a magnification of 2,000 times, no abnormal growth was observed at all.
ちなみに、PbTe基板上に上記の混晶比のPbTeS
e層を直接成長した場合のヘテロ接合体に同様の検査方
法を適用した場合はlc+a 当り約10”個の異常
成長部が認められた。By the way, PbTeS with the above mixed crystal ratio was deposited on a PbTe substrate.
When a similar inspection method was applied to a heterozygote in which the e-layer was directly grown, approximately 10'' abnormal growths were observed per lc+a.
以上説明せるとおり、本発明に係る半導体ヘテロ接合体
の製造方法にあっては、格子定数を異にする二つの半導
体(第1の半導体と第2の半導体)のヘテロ接合体を製
造する場合、
イ、上記二つの半導体の層の間に、第2の半導体の厚さ
数十へ程度の薄層と第1の半導体の厚さ数十人程度の薄
層との組を少なくとも1組入れることとし、
口、この組をなす薄層の層厚は、第1の半導体の薄層に
ついては、第1の半導体の層から第2の半導体の層に向
って次第に小さく、第2の半導体の薄層については、第
1の半導体の層から第2の半導体の層に向って次第に大
きくすることとされているので、格子定数を異にする2
種の半導体をもって格子整合された半導体ヘテロ接合体
の製造方法を提供することができる。As explained above, in the method for manufacturing a semiconductor heterozygote according to the present invention, when manufacturing a heterozygote of two semiconductors (a first semiconductor and a second semiconductor) having different lattice constants, B. Between the above two semiconductor layers, at least one set of a thin layer of the second semiconductor with a thickness of about several tens of nanometers and a thin layer of the first semiconductor with a thickness of about several tens of nanometers is inserted. , the layer thickness of the thin layers forming this set is such that the thickness of the thin layer of the first semiconductor gradually decreases from the thin layer of the first semiconductor toward the layer of the second semiconductor; As for
A method for manufacturing a lattice-matched semiconductor heterojunction using a seed semiconductor can be provided.
第1図は、本発明の構成説明図である。
第2図は、本発明の原理説明図である。
第3図は、本発明の詳細な説明図である。
■・・・第1半導体の層、 2・・・第2半導体の層
、 3.a〜3e・・・第2の半導体の薄層と第1の
半導体の薄層との組、 31・・舎弟1の半導体の薄層
、 32・・・第2の半導体の薄層。
本発明を所へ記
第1図
不ぢl3)lI久雰、理IB
第2図
1友地1万づ ・ 説明 1ンコ
第3図FIG. 1 is an explanatory diagram of the configuration of the present invention. FIG. 2 is a diagram explaining the principle of the present invention. FIG. 3 is a detailed explanatory diagram of the present invention. ■...First semiconductor layer, 2...Second semiconductor layer, 3. a to 3e... A set of a second semiconductor thin layer and a first semiconductor thin layer, 31... A thin layer of semiconductor 1, 32... A second semiconductor thin layer. Describing the present invention in Figure 1 (Figure 1) Figure 2 (1) Description Figure 3
Claims (1)
2の半導体とよりなる半導体ヘテロ接合体の製造方法に
おいて、 前記第1の半導体(1)と前記第2の半導 体(2)との間に、前記第2の半導体の薄層と前記第1
の半導体の薄層との組(3)を少なくとも1組形成し、 該薄層の組(3)のそれぞれを構成する各層の層厚は、
前記第1の半導体の薄層については前記第1の半導体(
1)に近接する側から前記第2の半導体(2)に近接す
る側に向って次第に小さくされ、前記第2の半導体の薄
層については前記第1の半導体(1)に近接する側から
前記第2の半導体(2)に近接する側に向って次第に大
きくされてなることを特徴とする半導体ヘテロ接合体の
製造方法。[Scope of Claims] A method for manufacturing a semiconductor heterojunction comprising a first semiconductor and a second semiconductor having a lattice constant different from that of the first semiconductor, comprising: the first semiconductor (1) and the second semiconductor; a thin layer of the second semiconductor (2) and the first semiconductor (2);
forming at least one set (3) with thin semiconductor layers, and the thickness of each layer constituting each of the set (3) of thin layers is as follows:
Regarding the thin layer of the first semiconductor, the thin layer of the first semiconductor (
1), the thin layer of the second semiconductor is gradually reduced in size from the side close to the first semiconductor (1) to the side close to the second semiconductor (2). A method for manufacturing a semiconductor heterojunction, characterized in that the size of the semiconductor heterojunction is gradually increased toward the side closer to the second semiconductor (2).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60176432A JP2520591B2 (en) | 1985-08-10 | 1985-08-10 | Method for manufacturing semiconductor heterojunction |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60176432A JP2520591B2 (en) | 1985-08-10 | 1985-08-10 | Method for manufacturing semiconductor heterojunction |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6236808A true JPS6236808A (en) | 1987-02-17 |
JP2520591B2 JP2520591B2 (en) | 1996-07-31 |
Family
ID=16013599
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60176432A Expired - Lifetime JP2520591B2 (en) | 1985-08-10 | 1985-08-10 | Method for manufacturing semiconductor heterojunction |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2520591B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190111746A1 (en) * | 2017-10-13 | 2019-04-18 | Honda Motor Co., Ltd. | Suspension device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6028268A (en) * | 1983-07-26 | 1985-02-13 | Agency Of Ind Science & Technol | Semiconductor device |
-
1985
- 1985-08-10 JP JP60176432A patent/JP2520591B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6028268A (en) * | 1983-07-26 | 1985-02-13 | Agency Of Ind Science & Technol | Semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190111746A1 (en) * | 2017-10-13 | 2019-04-18 | Honda Motor Co., Ltd. | Suspension device |
Also Published As
Publication number | Publication date |
---|---|
JP2520591B2 (en) | 1996-07-31 |
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