JPS6236267B2 - - Google Patents

Info

Publication number
JPS6236267B2
JPS6236267B2 JP54159885A JP15988579A JPS6236267B2 JP S6236267 B2 JPS6236267 B2 JP S6236267B2 JP 54159885 A JP54159885 A JP 54159885A JP 15988579 A JP15988579 A JP 15988579A JP S6236267 B2 JPS6236267 B2 JP S6236267B2
Authority
JP
Japan
Prior art keywords
address
signal
register
control
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54159885A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5587367A (en
Inventor
Jii Hootaa Marion
Daburyuu Nooman Juniaa Robaato
Ei Sherii Uiriamu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HANEIUERU INFUOOMEISHON SHISUTEMUSU Inc
Original Assignee
HANEIUERU INFUOOMEISHON SHISUTEMUSU Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HANEIUERU INFUOOMEISHON SHISUTEMUSU Inc filed Critical HANEIUERU INFUOOMEISHON SHISUTEMUSU Inc
Publication of JPS5587367A publication Critical patent/JPS5587367A/ja
Publication of JPS6236267B2 publication Critical patent/JPS6236267B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP15988579A 1978-12-11 1979-12-11 Cache memory Granted JPS5587367A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/968,312 US4245304A (en) 1978-12-11 1978-12-11 Cache arrangement utilizing a split cycle mode of operation

Publications (2)

Publication Number Publication Date
JPS5587367A JPS5587367A (en) 1980-07-02
JPS6236267B2 true JPS6236267B2 (en, 2012) 1987-08-06

Family

ID=25514052

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15988579A Granted JPS5587367A (en) 1978-12-11 1979-12-11 Cache memory

Country Status (3)

Country Link
US (1) US4245304A (en, 2012)
JP (1) JPS5587367A (en, 2012)
AU (1) AU531918B2 (en, 2012)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6429283U (en, 2012) * 1987-08-18 1989-02-21

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4345309A (en) * 1980-01-28 1982-08-17 Digital Equipment Corporation Relating to cached multiprocessor system with pipeline timing
US4433374A (en) * 1980-11-14 1984-02-21 Sperry Corporation Cache/disk subsystem with cache bypass
US4439829A (en) * 1981-01-07 1984-03-27 Wang Laboratories, Inc. Data processing machine with improved cache memory management
US4525777A (en) * 1981-08-03 1985-06-25 Honeywell Information Systems Inc. Split-cycle cache system with SCU controlled cache clearing during cache store access period
JPS58197553A (ja) * 1982-05-12 1983-11-17 Mitsubishi Electric Corp プログラム監視装置
US4714990A (en) * 1982-09-18 1987-12-22 International Computers Limited Data storage apparatus
EP0150177A1 (en) * 1983-07-11 1985-08-07 Prime Computer, Inc. Data processing system
US4573116A (en) * 1983-12-20 1986-02-25 Honeywell Information Systems Inc. Multiword data register array having simultaneous read-write capability
JPS6297036A (ja) * 1985-07-31 1987-05-06 テキサス　インスツルメンツ　インコ−ポレイテツド 計算機システム
US4766535A (en) * 1985-12-20 1988-08-23 International Business Machines Corporation High-performance multiple port memory
US4755936A (en) * 1986-01-29 1988-07-05 Digital Equipment Corporation Apparatus and method for providing a cache memory unit with a write operation utilizing two system clock cycles
US5010476A (en) * 1986-06-20 1991-04-23 International Business Machines Corporation Time multiplexed system for tightly coupling pipelined processors to separate shared instruction and data storage units
US5001665A (en) * 1986-06-26 1991-03-19 Motorola, Inc. Addressing technique for providing read, modify and write operations in a single data processing cycle with serpentine configured RAMs
US4768148A (en) * 1986-06-27 1988-08-30 Honeywell Bull Inc. Read in process memory apparatus
JPS6355636A (ja) * 1986-08-27 1988-03-10 Hitachi Ltd デ−タ処理システム
US5226169A (en) * 1988-12-30 1993-07-06 International Business Machines Corp. System for execution of storage-immediate and storage-storage instructions within cache buffer storage
US5073851A (en) * 1990-02-21 1991-12-17 Apple Computer, Inc. Apparatus and method for improved caching in a computer system
US5179672A (en) * 1990-06-19 1993-01-12 International Business Machines Corporation Apparatus and method for modeling parallel processing of instructions using sequential execution hardware
US5367648A (en) * 1991-02-20 1994-11-22 International Business Machines Corporation General purpose memory access scheme using register-indirect mode
US5261071A (en) * 1991-03-21 1993-11-09 Control Data System, Inc. Dual pipe cache memory with out-of-order issue capability
US5966514A (en) * 1995-05-31 1999-10-12 Matsushita Electric Industrial Co., Ltd. Microprocessor for supporting reduction of program codes in size
US6262936B1 (en) 1998-03-13 2001-07-17 Cypress Semiconductor Corp. Random access memory having independent read port and write port and process for writing to and reading from the same
US6262937B1 (en) 1998-03-13 2001-07-17 Cypress Semiconductor Corp. Synchronous random access memory having a read/write address bus and process for writing to and reading from the same
US6069839A (en) 1998-03-20 2000-05-30 Cypress Semiconductor Corp. Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method
US6873707B1 (en) * 2000-09-28 2005-03-29 Cisco Technology, Inc. Hardware-based encryption/decryption employing cycle stealing
US7006634B1 (en) * 2000-09-28 2006-02-28 Cisco Technology, Inc. Hardware-based encryption/decryption employing dual ported key storage
US6925534B2 (en) * 2001-12-31 2005-08-02 Intel Corporation Distributed memory module cache prefetch
US7389387B2 (en) * 2001-12-31 2008-06-17 Intel Corporation Distributed memory module cache writeback

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3806888A (en) * 1972-12-04 1974-04-23 Ibm Hierarchial memory system
CA1059639A (en) * 1975-03-26 1979-07-31 Garvin W. Patterson Instruction look ahead having prefetch concurrency and pipe line features
US4056845A (en) * 1975-04-25 1977-11-01 Data General Corporation Memory access technique
JPS5212536A (en) * 1975-07-21 1977-01-31 Hitachi Ltd Buffer memory control system
JPS5263038A (en) * 1975-10-01 1977-05-25 Hitachi Ltd Data processing device
US4156906A (en) * 1977-11-22 1979-05-29 Honeywell Information Systems Inc. Buffer store including control apparatus which facilitates the concurrent processing of a plurality of commands

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6429283U (en, 2012) * 1987-08-18 1989-02-21

Also Published As

Publication number Publication date
AU5262479A (en) 1980-06-19
JPS5587367A (en) 1980-07-02
US4245304A (en) 1981-01-13
AU531918B2 (en) 1983-09-08

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