JPS6235971A - Processing device for picture information of graphic display - Google Patents

Abstract

PURPOSE:To make processing of shifting and contracting in 1-2 vertical hours by sampling picture information sent out from an frame buffer in display giving corresponding addresses again on the picture, and storing in a waiting frame buffer. CONSTITUTION:On receiving a picture change position designating signal from a display processor 20, a command interpreting device 26 sends a sampling address to a comparator 28. On the other hand, a picture address indicator 24 detects a picture address being displayed by a synchronizing signal from a video interface 16 and sends to the comparator 28. When the two coincide, the comparator 28 a sampling command signal to a latch circuit 30 to take in and latch picture information read out at present. The latched data are written in a frame buffer 14b standing by. The amount of shifting is added to the written address at this time, and accordingly, the position on the picture is moved when this is read out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention provides multiplexed frame buffers for storing image information obtained by developing an image to be expressed in a bitmap format. The present invention relates to an image information processing device for a graphic display in which other image information is selectively written into the image information.

[Prior Art] Conventionally, this type of graphic display device has a basic configuration as shown in FIG.

This graphic display device includes a segment buffer 10 that holds data of an image to be expressed in units of segments, an image information development device 12 that develops the image data into image information on a bitmap, and an image information development device 12 that develops the image data into image information on a bitmap. A frame buffer 14 for storing the image information, a video interface 18 for converting the image information read from the frame buffer 14, and a CRT display 18 for displaying the image information converted to an analog signal as an image. and a display processor 20 for controlling the display processor 20.

This conventional display device has segment buffer 1
The information from 0 is analyzed and expanded in the image information expansion device 12 according to commands from the display processor 20 and sent to the frame buffer 14.

This frame buffer 144-J:, -11u is an image information storage unit having brains corresponding to inputs of a plurality of D/A converters, and sends image information to the video interface 1B at a constant cycle and displays it on the CRT display 18. The display is garish.

Incidentally, the efficiency of image processing largely depends on how quickly the information in the frame buffer can be changed while avoiding display operations.

In this case, since there is a limit to the response speed of the memory element, one of the measures for this problem is shown in FIG.

That is, this means divides the frame buffer 14 into a plurality of groups (here, 2 groups), including the buffer 14a currently being read and the buffer 14b on standby, and transmits the image information of the changed image to the buffer 14b on standby. After writing, the changed image is displayed by switching between the two.

Now, in one image processing, two-dimensional processing such as movement and reduction of the screen can be performed by changing the address of the information once developed in the frame buffer and sending it to the screen. The following method can be considered to perform this on the conventional graphic display shown in FIG. 5 mentioned above.

(a) Re-expand the information in the segment buffer and write it to the waiting frame buffer.

(b) While avoiding memory access for one display from the frame buffer being displayed, data is written to the buffer on standby through the image information development device while updating the address.

(C) A software change is made to the part that sends information from the frame buffer to the video interface at regular intervals for display, and the data is sent to a new on-screen address.

[Problems to be Solved by the Invention] However, the conventional methods have the following problems when implementing the above three means.

Regarding (a), it takes time to redeploy the information.

Regarding (b), since data is read from the brain being displayed, it is necessary to avoid the display period, which takes time.

Regarding (C), it is difficult to change the software because the display processor, image information development device, etc. are usually constructed using existing LSI.

The present invention was made in order to solve the above problems, and it samples the image information sent from the frame buffer being displayed to the video interface, reassigns the corresponding address on the screen, and transfers the image information to the waiting frame buffer. By storing the information in the CRT display, each movement and reduction process can be performed within 1 to 2 vertical hours of the CRT display, and there is no need to redeploy the information or avoid the CRT display period. Moreover, it is an object of the present invention to provide an image information processing device for a graphic display that can be easily changed.

[Means for Solving the Problems] The present invention provides multiple frame buffers for storing image information obtained by developing an image in bitmap format, and selectively transfers image information to frame buffers that are not currently being read. An image information processing device for a graphic display in which other image information is written, as shown in FIG. 1, sampling means for sampling image information to be changed from a frame buffer from which image information is currently being read. and.

write address setting means for setting a new write address for the sampled image information; and feedback control means for transferring the write address and the sampled image information to a frame buffer from which image information is not currently being read. It consists of

[Operation] In the above configuration, the sampling means detects the position of the image information to be changed from the frame buffer from which the image information is currently being read, and samples this.

The write address setting means sets a new write address for the sampled image information. For example, in the case of screen movement, this setting is performed by adding or subtracting the number of dots corresponding to the movement distance from the current address to set a new address for writing.

The feedback control means transfers the address to be newly written and the sampled image information to a frame buffer from which image information is not currently being read, ie, a buffer on standby.

As a result, the changed image information will be written into the waiting buffer. Then, by switching the reading of image information from the buffer currently being read to the buffer on standby, a new, changed image is displayed on the CRT screen.

Note that if you configure the frame buffer with multiple planes and write images independently to each plane, you can easily create videos, etc. by changing only the image of a specific plane and overlapping it with other planes. can.

[Example 1 Embodiments of the present invention will be described with reference to the drawings.

<Configuration of Embodiment> FIG. 2 shows a graphic display equipped with an embodiment of the image information processing apparatus of the present invention.

The graphic display shown in FIG. 2 includes a segment buffer lO that holds data of an image to be expressed in units of segments, an image information development device 12 that develops the image data into image information on a bitmap, and an image information development device 12 that develops the image data into image information on a bitmap. Frame buffer 14a, 1 stores image information
4b, a video interface 16 for D/A converting the image information read from the frame buffers 14a and 14b, a CRT display 18 for displaying the image information converted into an analog signal as an image, and a display for controlling each of the above parts. and a processor 20. Note that these configurations are the same as those shown in FIGS. 4 and 5 of "-2", so the explanation will not be repeated.

Further, this graphic display is connected to a selector 32 for connection with the image information processing device 22 of this embodiment.
and two frame buffers 14a and 14b in L.
and a display plane selection device 34 that performs switching. The selector 32 selects the address and data from the image information development device 12 and the address and data from the image information processing device 22. This selection command is
Based on the command sent from the image information processing device 22. Display plane selection device '1134, frame buffer 1
For 4a and 14b, either read or write (
(standby) system. This switching command is based on a command sent from the image information processing device 22.

The image information processing device 22 detects the address of the currently displayed screen based on the synchronization signal from the video interface 16, and also includes a screen address instruction device 2 that instructs the address of the screen currently being displayed.
4, a command interpretation device 26 that receives commands, screen change variables, plane instructions, etc. from the display processor 20, interprets these, and executes them; and an address specified to the screen address instruction device 24 is a command A comparator 28 compares whether or not the sampling position is specified by the interpretation device 2B and outputs a sampling instruction signal when they match, and when receiving the sampling instruction signal from the comparator 28, the frame buffer 14a, 14b that is being read (
In FIG. 2, it is configured to include a latch circuit 30 that holds image information from the eye a).

As shown in FIG. 3, the command interpreter 26 includes a command interpreter 36 that interprets commands from the display processor 20 and outputs various instruction signals, and a selector based on the instruction signals from the command interpreter 3B. a selector switching signal generator 38 that generates a switching signal of 32, and a display brain designator that sends a switching command to the display brain selection device 34 based on the plane designation signal from the display processor 20 and the switching signal from the command interpreter 3B. section 40, a sample address generation section 42 that sends a sampling address to the comparator 28 based on the image change position designation signal from the display processor 20 and the change command signal from the command interpretation section 38, and a sample address generation section 42 that newly writes the changed image. and a write address generation section 44 to be written.

The sample address generator 42 receives the range to be sampled and the sampling density from the display processor 20. The sampling density is set to the sampling rate for the dots on the screen constituting the image to be sampled, for example, 1 in the case of movement, and the reduction rate 1/n in the case of reduction. The sample address generator 42 forms a sample address from this density and the range to be sampled.

The write address generation unit 44 receives a variable for changing the image, for example, changing the position, from the display processor 20, performs an operation on this and a sample address or an address designated by the display processor 20, and performs a calculation to change the image. Generates a write address that specifies the location where the new image should be written.

The screen address instruction device 24, the comparator 28, the latch circuit 30, and the sample address generator 42 constitute sampling means for sampling image information to be changed from the frame buffer. Further, the sample address generation section 42 and the write address generation section 44 are
A write address setting means is configured to set a new write address for the sampled image information. Further, the selector switching signal generating section 38 and the display brain specifying section 40 constitute feedback control means for transferring the write address and sampled image information to the standby frame buffer.

<Operation of the embodiment> The operation of the embodiment will be explained with reference to the L-graph.

To write image information as a normal operation in a graphic display equipped with the image information processing device of this embodiment, first, the display processor 20 converts the image information stored in the segment buffer 10 together with a command. The data is sent to the device 12, where it is expanded into a bin map.

The information is then passed through the selector 32 to the frame buffer 14b that is not being read at that time, that is, is on standby.
write to. During this time, image information is read out from the other frame buffer 14a, supplied to the CRT display 18 via the video interface 18, and displayed as an image.

Next, a case will be described in which a part of the currently displayed screen is moved to another part.

In this case, based on the image change position designation signal from the display processor 20 and the change command signal from the command interpreter 38, the sample address generator 42:
A sampling address is sent to the comparator 28.

This address is sequentially output for all dots to be sampled on the screen.

On the other hand, the screen address instruction device 24 detects the address of the currently displayed screen based on the synchronization signal from the video interface 1B, and instructs the comparator 38 to detect the address of the screen currently being displayed.

The comparator 38 receives an address indicating the position of the screen currently being displayed, which is sequentially sent from the screen address indicating device 24, and compares this with the sampling address. When the two match, the comparator 38 sends a sampling instruction signal to the latch circuit 30 to capture and latch the image information currently being read from the frame buffer 14a.

When the latch circuit 30 receives the sampling instruction signal from the comparator 28, the frame buffer 14a,
14h being read (14a in Figure 2)
) and retains the image information.

Here, the write address generation unit 44 receives variables for changing the position of the image from the display processor 20. This variable is given as the amount of movement (for example, the address difference of the dot matrix on the screen). The write address generation unit 44 adds the screen address and the address difference, which is a variable, and sends this result to the selector 32 as a write address. At the same time, the image information held in the latch circuit 30 is sent to the selector 32 as write data.

In the selector 32, a switching signal sent from the selector switching signal generating section 38 based on the instruction signal from the command interpreting section 36 causes the address and data described in "2" to be partially replaced by the image information development device 12. It becomes writable.

Also, at this time, the display plane selection device 34 selects the frame buffer 14a based on the command from the display plane specifying unit 40.
Read system, frame buffer + 4b t-write (
Since this is a standby (standby) system, the above address and data are written to the latter.

Thereafter, the display plane selection device 34 outputs the changed and written image information by setting the frame buffer 14a as a writing (standby) system and setting the frame buffer +4b as a reading system according to a command from the display plane specifying unit 40. is possible.

Next, a case will be described in which a part of the currently displayed screen is reduced and displayed.

The sample address generation unit 42 receives from the display processor 20 a reduction rate of 1/n for image reduction as a sampling density. Data sample addresses are then sequentially formed in increments of n in both the horizontal and vertical directions and sent to the comparator 28.

The comparator 28 compares the sequentially sent data sample addresses with the address indicating the position of the currently displayed screen that is sequentially sent from the screen address instruction device 24, and if they match, the data at that address is transferred to the latch circuit. 30 and hold it.

The write address generation unit 44 uses a reduction rate of 1/n for image reduction as a variable for changing the image.

The information is received from the display processor 20. The write address generation unit 44 uses the center of the screen as the origin, and when the screen address for that point is (X, Y), (X/n).

Y/n) is generated. Then, this 7-dress is sent to the selector 32 together with the image information to be written, and is written into the standby frame buffer 14b as in the case of two-legged movement.

After this, the process is the same as in the case of moving the image above.

<Modification of Embodiment> In the embodiment described above, a case is shown in which two systems of frame buffers are used, but three or more systems may be used.

[Effects of the Invention] As explained above, the present invention samples the image information sent from the frame buffer currently being displayed to the video interface, resets the corresponding address on the screen, and transfers the image information to the waiting frame buffer. By storing C
Each movement and reduction process can be performed in 1 to 2 vertical hours of the RT display, and there is no need to redeploy information or avoid the CRT display period, and it is easy to change. It has the effect of

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an image information processing device of the present invention, FIG. 2 is a block diagram showing an embodiment of the image information processing device of the present invention, and FIG. 3 is a command interpretation device used in the above embodiment. FIG. 2 is a block diagram illustrating the configuration of a professional method. 10...Segment buffer 12...Image information expansion device 14.14a, 14b = 7 +y-mbar-/
7716...Video interface 18...CRT display 20...Display processor 22...Image information processing device 24...Screen address instruction device 26...Command interpretation device 28...Comparator 30... Latch circuit 32...Selector

Claims (1)

[Claims] Multiplexed frame buffers are provided to store image information obtained by developing the image to be expressed in bitmap format, and other image information is selectively written to the frame buffers from which image information is not currently being read. An image information processing device for a graphic display in the form of a sampling means for sampling image information to be changed from a frame buffer from which image information is currently being read, and setting a new write address for the sampled image information. and feedback control means for transferring the write address and sampled image information to a frame buffer from which image information is not currently being read. Information processing device.