JPS6235705B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a main memory configuration control device in an information processing device. In particular, it relates to transition control between a dual storage state and a single storage state for the same data in main memory.

[Conventional technology]

Conventionally, in an information processing device configured to be able to store the same data in two main memory devices in duplicate, the main memory controller has a single memory controller and two main memory controllers.
A method is adopted in which a dual storage control section is provided which generates the same command twice in the main storage device of the main storage device, and one of the control sections is selected by designating an external switch.

However, when switching from a single storage state to a dual storage state, simply switching and selecting the dual storage controller does not bring the two main storage devices into a synchronous operating state, so the dual storage controller Duplicate commands may not be possible.

An example of this type of information processing apparatus will be explained using the one shown in FIG.

FIG. 1 is a block diagram of the main parts of a conventional device. Connected to the main storage control device 1 are logical devices 2 ₁ and 2 ₂ and main storage devices 3 ₁ and 3 ₂ , respectively. That is, logical unit 2 ₁ and 2
₂ and the outputs from main storage devices 3 ₁ and 3 ₂ are respectively guided to a request receiving circuit 5 within main storage control device 1 . The output of an external switch 6 is led to this request receiving circuit 5. One output of this request receiving circuit 5 is led to a dual storage control section 7, and the other output is led to a single storage control section 8.

This dual storage control section 7 and single storage control section 8
The outputs of are respectively led to request sending circuits 9. The output of the request sending circuit 9 is led to main storage devices ₃₁ and ₃₂ , respectively.

Further, in FIG. 1, A ₁ to A ₁₁ indicate various input or output signals, respectively.

The operation of such a conventional device will be explained. Memory request outputs A ₁ , _{A 2} from the logic devices 2 1 , 2 ₂ are sent to the request receiving circuit 5 . Dynamic RAM refresh request outputs A ₃ and A ₄ from the main storage devices 3 ₁ and 3 ₂ are also sent to the request receiving circuit 5 . The request receiving circuit 5 responds to the memory request according to the value of the single storage state and dual storage state switching signal _A11 output from the external switch 6.
A ₁ to _{A 4} are sent as a command A ₅ to the dual storage control section 7 or a command A ₈ to the single storage control section 8 .
The dual storage control section 7 generates a dual write/read command _A7 in response to the memory request command _A5 . The single storage control unit 8 generates a single write/read command _A8 in response to the memory request command _A6 .

In the request sending circuit 9, the double write read command
When A ₇ is sent, memory request commands A ₉ and A ₁₀ are sent to the two main storage devices 3 ₁ and 3 ₂ . Further, when the single write/read command A ₈ is sent, the memory request command A ₉ or A ₁₀ is sent only to the corresponding main storage device 3 ₁ or 3 ₂ .

[Problem that the invention seeks to solve]

In such a conventional device, a signal for switching the single storage control state to the dual storage state is sent from the external switch 6.
After A ₁₁ is input and the request receiving circuit 5 is designated to the dual storage state, by chance, a dynamic RAM refresh request A ₃ is sent from the main storage device ₃₁ .
may be output. This refresh command A ₃ is transmitted to the dual storage control section 7 , and the dual storage control section 7 outputs a double write command A ₇ to the request sending circuit 9 . As a result, main storage device 3 ₁
A refresh command is output to both 3 and ₂ . In other words, the refresh command is erroneously transmitted to the main storage device ₃₂ to which no refresh request has been generated at a timing inappropriate for refresh.

As described above, in conventional devices, the transition from the single storage state to the dual storage state is not synchronized with the operation of the main storage device, so depending on the timing, the operation of the main storage device may be disrupted. It was hot.

The present invention improves this point, and provides an information processing device that can correctly set the timing of storage state transition and also allows the main storage device to perform synchronous processing operations when performing dual storage. With the goal.

[Means for solving problems]

In the present invention, a control output is connected to two main storage devices that can perform dual storage of the same data,
a receiving circuit that receives a request for a logic circuit that generates a read or write request to the main memory along with a dual storage instruction or a single storage instruction as a program is executed; If dual storage is commanded from , then writing/reading is controlled for each of the two main storage devices, and if single storage is commanded, writing/reading is controlled for one of the two main storage devices. In a main memory control device including means for sending out a control output, the receiving circuit includes means for prohibiting reception of a request from the logic circuit according to a prohibition instruction, inputs the dual storage instruction, and receives the dual storage instruction. A state transition control circuit is provided that outputs an instruction to set the two main storage devices to an initial state and the prohibition instruction to the receiving circuit, and the state transition control circuit includes:
means for transmitting a command to prohibit reception of the request for the time required to process the immediately preceding command when a double storage command is input; and means for generating a command to set the initial state after this time has elapsed. It is characterized by including.

[Effect]

The device of the present invention is equipped with a state transition control circuit, and when transitioning from a single storage state to a dual storage state, when a transition command is input, reception of new commands from the logic circuit is prohibited. do. During this time, the commands that have been given so far are processed, and then the two main memories are simultaneously set to the initial state. Subsequently, the above-mentioned prohibited state is canceled and a double storage state is established. Therefore, when transitioning to the dual storage state, the two main storage devices are in a synchronous state, and as a result of this transition, refresh commands and other commands being processed are no longer erroneously transmitted.

〔Example〕

An embodiment of the present invention will be described based on the drawings.

FIG. 2 is a block diagram of essential parts of an embodiment of the present invention. The device is characterized in that a state transition control circuit 12 is provided to control the timing of transition to the single and dual storage states, and to set the synchronization state of the main storage device in the dual storage state.

That is, the transition instructions I ₁ and I ₃ from the single storage state to the dual storage state of the logic devices 2 ₁ and 2 ₂ are executed by the OR gate 1 in the state transition control circuit 12, respectively.
Enter 3. In addition, instructions I ₂ and I ₄ for transitioning the logic devices 2 ₁ and 2 ₂ from the dual storage state to the single storage state are input to the OR gate 14 in the state transition control circuit 12, respectively. The output H ₁ of the OR gate 13 is led to the set terminal of the flip-flop 15. The output of this flip-flop 15
_H2 is led to a counter 16 which stops counting when a preset count value is reached and sends out a count-up output _H3 . This counter 1
The output _H3 of 6 is led to the set terminal of flip-flop 17. The output _H4 of flip-flop 17 is led to the set terminal of flip-flop 18. The output of the OR gate 14 is led to the reset terminal R of the flip-flop 18.

Further, the output _H2 of the flip-flop 15 is input to the request receiving circuit 5. The output _H4 of the flip-flop 17 is sent to the main memory 3.
₁ and ₃₂ as initial state setting inputs, and is also input to reset terminals R of flip-flops 15 and 17, respectively. Further, the output _H5 of the flip-flop 18 is led to the request receiving circuit 5 as a control command for canceling the inhibition and for controlling the double storage state.

The characteristic operation of the present invention will be explained using such a circuit configuration.

While the output _H2 of the flip-flop 15 led to the request receiving circuit 5 is at logic "1", reception of memory requests _A1 to _A4 is prohibited. Therefore, once flip-flop 15 is set, reception of new memory requests is inhibited until reset by the output _H4 of flip-flop 17.

The counter 16 of the state transition control circuit 12 receives the signal
Outputs signal _H3 when a predetermined time has elapsed since _H2 was input. This signal _H3 sets flip-flop 17. Flip-flop 17 is immediately reset by its output _H4 . Therefore, after the predetermined time has elapsed since the signal _H2 is applied to the request receiving circuit 5 and the reception of new requests is prohibited, a short pulse signal is sent to the main memories ₃₁ and ₃₂ . H ₄ is given at the same time. Furthermore, when the flip-flop 18 rises, its output signal _H5 is input to the request receiving circuit 5. The predetermined time set in the counter 16 is a value greater than or equal to the maximum time required from when an instruction is input to the main memory control device 1 until the instruction is processed and output, and when a new request is received. After being prohibited and before the next action is taken,
Ensure that no unprocessed instructions remain in this device.

Here, transition control between the dual storage state and the single storage state, which is a feature of the present invention, will be explained. When the first instruction _I1 is output from the logic device ₂₁ or ₂₂ , the OR gate 13 of the state transition control circuit 12
A logic "1" output H1 is sent from the flip-flop ₁₅ , and the flip-flop 15 is set. flipflop 1
When 5 is set, the counter 16 is activated by this output _H2 . The output _H2 of this flip-flop 15 is the request receiving circuit 5 of the main memory 1.
It can also be conveyed. As a result, the request receiving circuit 5 operates to block reception of memory requests A ₁ , A ₂ , A ₃ and A ₄ until the flip-flop 15 is reset. This reception blocking time is determined by the counter 16.
Since the time period is set to be sufficiently long, the main storage devices ₃₁ and ₃₂ will be in a state in which all the memory requests being processed have been completed during that time. When the count of the counter 16 is completed, the flip-flop 17 is set by the count-up output _H3 . The output H ₄ of flip-flop 17 sets flip-flop 18 and resets flip-flops 17 and 15.

Further, the output H ₄ of the flip-flop 17 is simultaneously sent to the main memories 3 ₁ and 3 ₂ for a certain period of time to bring the main memories 3 ₁ and 3 ₂ into a common initial state. As a result, main storage devices 3 ₁ and 3 ₂
are in the initial state synchronously, so as long as the requests A ₉ and A ₁₀ from the main storage device 1 occur synchronously,
Its operating state is synchronized. Therefore, the timing of occurrence of refresh requests A ₃ and A ₄ is also synchronized. Also, when the flip-flop 18 is set by the output _H4 of this flip-flop 17, this output
_H5 is transmitted to the request receiving circuit 5 and acts to select the dual storage controller 7. Therefore, from now on, the main memory access requests A ₁ to _{A 4} are controlled by the dual memory control unit 7, and the same commands are synchronously transmitted to the main memory devices 3 ₁ and 3 ₂ , respectively.

Further, when the second instruction _I2 is sent from the logic device ₂₁ , the flip-flop 18 is reset by the output of the OR gate 14 in the state transition control circuit 12, and the main memory controller 1 changes from the dual memory state to the single memory state. to move to.

〔Effect of the invention〕

As explained above, according to the present invention, the main memory control device blocks memory requests until the main memory completes processing, and simultaneously initializes the main memory in a synchronous state at the same time as transitioning to the dual storage state. I decided to do so.

Therefore, there is no difference in the transition timing from the single storage state to the dual storage state between the two main storage devices, and a refresh request for one memory is not executed in the other main storage device by mistake. There is no chance that it will happen. Further, even in the dual storage state, the main storage device can perform processing operations in a synchronous state, and the reliability of processing operations can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main parts of a conventional device. FIG. 2 is a block diagram of a main part of an embodiment of the present invention. 1... Main memory control device, 2 ₁ , 2 ₂ ... Logical device,
3 ₁ , 3 ₂ ...Main storage device, 5...Request receiving circuit, 6...External switch, 7...Double storage control unit,
8...Single storage control unit, 9...Request sending circuit,
12... State transition control circuit, 13, 14... OR gate, 15, 17, 18... Flip-flop, 16
…counter.

Claims (1)

[Claims] 1. Double storage of the same data is possible. 2.
A control output is connected to the main storage devices 3 ₁ and 3 ₂ of the main storage devices, and as a program is executed, a read or write request to the main storage device is sent as a dual storage command.
A receiving circuit 5 is provided for receiving a request of the logic circuits 2 ₁ , 2 ₂ occurring with an instruction I ₁ , I ₃ or a single storage instruction I 2 , I _{4 ,} wherein a double storage is commanded from the logic circuit. For example, if single storage is commanded for the two main storage devices, the main storage device includes means for sending a control output for controlling write/read operations to one of the two main storage devices, respectively. In the main storage control device, the receiving circuit includes means for prohibiting reception of requests from the logic circuit according to a prohibition instruction _H2 , inputs the dual storage instruction, and transmits the instruction to the two main storage devices. A state transition control circuit 12 is provided which outputs an instruction _H4 to set the ``initial state'' and the prohibition instruction _H2 to the receiving circuit. The main body characterized in that it includes means for sending an instruction _H2 for prohibiting the reception of the request for the time required to process the instruction, and means for generating an instruction _H4 for setting the initial state after the elapse of this time. Storage controller.