JPS6235560A - Mis type semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent a software error of alpha-rays by forming a groove of a buried capacitor irregularly to extend the peripheral length, thereby obtaining necessary charge holding capacity. CONSTITUTION:A MOS transistor which forms a memory cell is composed of impurity diffused layers 9A, 9B to become source and drain regions formed on a semiconductor substrate, and a gate electrode which also operates as a word line 2. A capacitor is formed with the substrate as one capacitor electrode and a polycrystalline silicon 1 buried in a groove 5A through a capacity insulating film 8 formed on the surface of the groove 5A formed along a groove pattern 5 on the substrate 7 as the other capacitor electrode. The groove 5A of the capacitor buried with the silicon 1 is formed in a pectinated shape in the vertical direction. Since the capacitor is formed mainly at the side wall of the groove formed in the pectinated shape, the charge holding capacity of the capacitor can be increased as compared with the conventional one.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an MIS type semiconductor memory device, and particularly to a one-transistor, one-capacitor type MIS in which a capacitive part is provided in a groove.
The present invention relates to a type semiconductor memory device.

[Conventional technology]

Conventionally, as the scale of storage StO of a memory device increases, the area of its memory cell has been reduced.

However, in this case, if the shape of the memory cell is simply reduced, the area of the Nt portion will be reduced, and the amount of charge that can be stored will also be reduced, leading to the problem of soft errors due to alpha rays. For this reason, a method has been proposed and implemented in which the side surface of a monument formed in the same direction as the semiconductor substrate is used as a capacitor portion.

FIGS. 3(a) and 3(i) are a plan view of an example of a conventional MIS type semiconductor memory device in which a capacitive portion is formed in a trench, and FIG.
It is a sectional view taken along the line A'.

In Fig. 3 ta) t tbJ, the MOS transistor has an impurity diffusion layer 9 forming the source/drain region.
A, 9B and the gate polarization 28, etc., which run through the word line 2, and the capacitor section connects the semiconductor substrate 7 to one side.
t 'JL sM, and the entire polycrystalline silicon 1 buried thereon is interposed through an insulating film 8 as a dielectric film provided on the surface of d5A formed along the groove pattern 5 on this semiconductor substrate 7. It is formed as a valley cap electrode on the pond side. That is, the capacitive portion is composed of a planar valley portion on the semiconductor substrate 7 and a side surface portion in the groove.

In Fig. 3 (ta), (bl), 3 is a contact hole, 4 is an insulator buried in the isolation trench 5B separating memory cells, and 6 is an impurity diffusion node of the same conductivity type as the semiconductor substrate 7. , 8A, 11 smells, 10 is the focus line.

[Problem that the invention seeks to solve]

However, when the following memory cell described above is used in a MIS type semiconductor memory such as a higher-density random access memory, the reduction of the B-:'i part by 1 is f I don't have one. As a result, charge retention is reduced, and α
This has the disadvantage that soft errors due to lines are more likely to occur again.

One possible solution to this reduction in charge storage capacity is to increase the roughness of the monument in which the capacitor portion is formed. However, microfabrication techniques such as etching are within the range of t@ and naturally have their limits.

SUMMARY OF THE INVENTION An object of the present invention is to provide an MIS type semiconductor memory device that increases the charge retention capacity t without increasing the depth of the groove in which the capacity is formed, and prevents the occurrence of error caused by α rays. be.

[Means to solve all problems]

The M I S type convoluted storage device of the present invention is a capacitive S type semiconductor storage device including a MOS transistor formed on a semiconductor substrate and a capacitive part connected to the MOS transistor and formed in a groove. The groove in which the groove is formed has an uneven planar shape.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a first embodiment of the invention.

The difference from the conventional example shown in FIG. 3 (aJ) is that when the groove formed in the volume of the semiconductor substrate is viewed from above, the shape of the flllU wall is embedded in the isolation groove.

Note that the sectional view taken along the line BB' of this embodiment 1 is almost the same as that of FIG. 3 tb+, so the description will be made with reference to FIG.

In FIG. 1 and FIG. 3 tbl, the MOS type transistor constituting the memory cell is formed on the semiconductor substrate 7 with a non-porous extension +m9A, 9 which becomes the north drain region.
B, a gate electrode 28 which also serves as the word line 2, and the like. The capacitor portion is provided with a container P! on the surface of a groove 5A formed along the groove pattern 5 on the semiconductor substrate 7, using the semiconductor substrate 7 as one capacitor electrode. , polycrystalline silicon 1 buried in the groove 5A via the edge pA8 is formed as the other volume electrode. The polycrystalline/Recon 1 was used to form the Tanisetto 5A in the form of an fω shape in the vertical direction.

In FIG. 1, reference numeral 4 indicates an isolation trench 5B for separating memory cells.
It was buried in the area and the edge → it is obvious.

In this embodiment 2, which has been formed in this manner, the capacitor portion is mainly formed on the side wall portion of the neck, which is formed horizontally, so that the charge retention capacity of the valley catch portion can be made smaller than in the conventional case. It is possible to write.

FIG. 2 is a plan view of a second embodiment of the present invention, in which the load 5A of the capacitive part filled with polycrystalline silicon 1 is formed into a box shape in the vertical direction. This embodiment also has the same effect as the case of FIG. 1.

In order to manufacture the MIS type semi-integrated storage device shown in FIG. 1 or FIG.
All you have to do is change the mask pattern for forming the grooves fL,
There is no need to add other steps.

〔Effect of the invention〕

As explained above, the present invention provides the necessary
This has the effect of ensuring sufficient storage space and preventing soft errors due to the small size of the memory cells.

[Brief explanation of drawings]

FIG. 1 is a plan view of a first embodiment of the present invention, FIG. 2 is a 101i'TT diagram of the second embodiment of the present invention, and FIG. 3(a). (bl is a plan view of a conventional MIS type semiconductor memory device and M
In the front view, Hi Ru. 1... Polycrystalline silicon, 2... Word line, 3... Contact hole, 4... Loquat, 5... - Tsumugi Pattern, 5A...Groove,
5B...Separation groove, 6...Non, autopsy expansion +m%7...Semiconductor substrate, 8...Capacitive insulating film, 8A... ...Interlayer insulating film, 9 A, 9
B... Impurity diffusion layer, 10... Bit line. Agent Patent Attorney Uchihara Otokyo 2 ShiI

Claims (1)

[Claims] A MOS transistor formed on a semiconductor substrate and the M
In an MIS type semiconductor memory device having a memory cell including a capacitive part connected to an OS type transistor and formed in a trench, and an isolation trench in which an insulator is buried to separate the memory cells, the capacitive part is formed. An MIS type semiconductor memory device, wherein the groove is formed to have an uneven planar shape.