JPS623529A - Automatic gain control circuit - Google Patents

Abstract

PURPOSE:To stabilize the pull-in operation by providing a means receiving an output of a multi-value identifier and discriminating the 1st region - 3rd region set to include the outermost point and the innermost point to a demodulation signal and a means applying logic operation to an output of the discrimination means. CONSTITUTION:The demodulation signal enters an A-D converter via a variable attenuator (ATT) 1 and a subtractor 18 and converted into data strings D1-D4. In the A-D converter 2, when a demodulation signal with normal level represented by d1-d8 in figure is inputted, signals D1-D4 shown in the right side in figure are outputted. A logic circuit A forms an error signal and the regions 1-3 are provided and when the demodulation signal enters the regions 1 and 3, the ATT 1 is controlled to increase the demodulation signal, and when the demodulation signal enters the regions 2, a control signal is outputted to the ATT 1 to decrease the demodulation signal. The demodulation signal continues to be increased by the ATT 1 until signals d1' and d8' enter the regions 1 and 3 and becomes stable at the points of d1-d8. Thus, no pseudo pull-in state is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic gain control circuit that sets the input level of a multi-value discriminator to an optimum level in a demodulator applied to a multi-value transmission system.

[Conventional technology]

In recent years, various microwave digital transmission systems have been put into practical use, and at present, a high multilevel orthogonal amplitude modulation system capable of high-density transmission is often employed. This method allows a large amount of information to be transmitted, but the configuration becomes more complex and the characteristics required of the circuit become stricter. As one of these, automatic gain control characteristics are set in the demodulator in order to maintain the demodulated multilevel signal at the optimum level for the multilevel discriminator, and very strict characteristics are required. As a configuration that can meet this requirement, two "
"Automatic Gain Control Circuit" (Japanese Patent Application No. 56-015776). According to this method, the input level of the multi-level discriminator is strictly set to the optimum level, but a pseudo-entrainment phenomenon may occur during the entrainment process. There is a drawback that the pull-in phenomenon does not occur, and as a result, the correct main data signal cannot be reproduced.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic gain control circuit that can perform stable pull-in operation by eliminating the occurrence of the pseudo pull-in phenomenon caused by the prior art.

[Structure of the invention]

An automatic gain control circuit according to the present invention sets an input level of a multi-value discriminator to an optimum level in order to perform multi-value discrimination of a multi-value baseband signal. An IF' band or baseband variable attenuator is inserted to change the input level of the multi-level discriminator, and receives the output of the multi-level discriminator, and A logical operation is performed on the output of the determination means or the output of the determination means including the multi-value discriminator, and a means for determining a first region to a third region set to include inner points.

and logic means for generating a control signal for controlling the variable attenuator.

[Conventional example]

Here, to facilitate comparison between the two inventions.

A conventional automatic gain control circuit will be explained with reference to the block diagram of FIG. In this figure, 1 is a baseband variable attenuator (ATT), 2 is a 41:00 cut A-D converter, 3 is an EX-OR circuit, and 4 is a low-pass filter (LPF). The input signal is an 8-value baseband signal and is input to the A-D converter 2 via the ATT 1. Here, D1 to D3 are reproduced as main data signals, and D4 is reproduced as an error signal. and D4 is EX −
The OR circuit 3 performs an EX-OR operation to obtain C1. This CI is used as a control signal to suppress the knock component.
F 4 to ATT 1 and A-D converter 2
The input level of is controlled to the optimum value.

FIG. 3 is a diagram for explaining the operation of the conventional example.

In the figure, dl to d8 represent 8-value baseband signals,
C1 represents output data of the EX-OR circuit 3.

Here, when the input data d1 to d8 deviate from the center OV, that is, when the demodulation level becomes large, the CI
All outputs are 0'', and vice versa, they are 1''.

Therefore, it can be seen that the output of CI is an error signal of the automatic gain control circuit. Next, the pseudo entrainment phenomenon will be explained. Now, in the initial state, the demodulated signal d (represented by d1' to d8' in the figure) has a value of 7/9 of the normal 1/pel.
; Assuming that it is input to the A-D converter 2, the CI multiplied signal,
'0' and '1' outputs will be output with equal probability, and even though the level of the demodulated signal is not the normal level, the error signal will appear stable, and the demodulated signal will return to the normal level. In this way, when the demodulated signal enters d1' to d8' in the figure, it cannot be extracted from there and a pseudo pull-in phenomenon occurs.

EMBODIMENTS OF THE INVENTION FIG. 1 is a block diagram showing an embodiment of an automatic gain control circuit according to the present invention. In this figure,
2 and 4 have the same functions as those of the conventional example shown in FIG. 5 is a low pass filter (LPF), 6 is a logic circuit (4), and 7 is a logic circuit (B).

8.9 is a selection circuit, 10.11 is a flip-flop circuit, 12 to 15 are OR/NOR circuits, 16.17 is a circuit, and 18 is a subtracter. In this circuit, the demodulated signal passes through ATT 1 and subtracter 18, enters AD converter 2, and is converted into data strings D e D 1 to D4. A-
The D converter 2 outputs signals D1 to D4 shown on the right side of FIG. 2 when demodulated signals of normal levels shown as d1 to d8 in FIG. 3 are input. The logic circuit (4) 6 is for creating an error signal, which is a feature of the present invention.

Regions 1-3 are provided as shown in FIG.

When the demodulated signal enters regions 1 and 3, A'l"T I
To make the demodulated signal thicker by controlling
d4 and d5 in area 2.

It is stabilized in a state where d8 is in contact with region 3, that is, in a normal state shown in FIG. Also, as an initial state, ar-d
When the demodulated signal of s' is input to the A-D converter 2, d
4' and d5' fall into region 2.

There are no signal points that fall into regions 1 and 3. for that.

The demodulated signal continues to increase by ATT 1 until d1' and d8' enter regions 1 and 3, then dl~d8
It is stable at this point. Therefore, a pseudo-retraction state does not occur.

Referring to FIG. 1, signal b1 is "1" for regions 1 and 3.
'', the flip-flop circuit 10 is reset and its output becomes ``0''. Also, the signal b2 becomes ``1'' for area 2, and the flip-flop circuit 10 is sent to set its output to 1#. shall be. Here, if logic ``'1#'' is a positive voltage and logic ``0#'' is a negative voltage, then ATT
If 1 has a characteristic that the attenuation amount is small at a positive voltage and the attenuation amount is large at a shear negative voltage, the above-mentioned act like you did. The circuit composed of the logic circuit (B) 7 and the subtracter 18 compensates for the DC drift included in the demodulated signal at the input of the A-D converter 2, and its operation is based on the "DC drift" in the application filed by the present inventor. ``Voltage control circuit'' (patent application 1973)
8-48249), please refer to it. It is desirable to use two of these DC voltage control circuits in order to properly operate the automatic gain control circuit according to the present invention.

Not essential.

In FIG. 3, regions 1 to 3 are shown for an 8-level demodulated signal, where region 1 is a region circumscribing dl, and region 2 is an region inscribed in d4-d5.

Region 3 is a region circumscribing d8, but as the demodulated signal increases in number of multi-values such as 16 values, setting regions 1 to 3 with only the outermost point and innermost point makes it easier to use for control. If the number of signal points that can be generated is too large, and therefore the number of multilevel values increases, the advantages of the present invention can be maintained and used for control by expanding the area to several points including the outermost point and the innermost point. The signal can be increased. In addition,
36th life. A:ζLmuwiνyu. Roaaaa.

FIG. 5 shows an example of a 64 QAM demodulation device used in the present invention. In this figure.

19 is a variable attenuator for the IF band, and 20 is a quadrature detector.

21 and 22 are subtracters, 23 and 24 are 4-bit AD converters, 25 is an adder, 26 is a logic circuit, and 27 is a voltage controlled oscillator (VCO). According to this example.

The 64 QAM modulated wave enters the quadrature detector 20 via the IF band variable attenuator 19, where it is quadrature detected and becomes an 8-value demodulated signal represented by P and Q.

Since the P and Q signals are exactly the same as the input signals in FIG.
It is. However, the difference is that after the outputs of the two selection circuits 8p9 are added by the adder 25, the IF band variable attenuator 19 provided in common with ppQ is controlled. still.

The variable attenuator 19 may be provided individually in the P and Q baseband bands, or one baseband variable attenuator and one IF band variable attenuator may be provided in either P or Q. You can also take it. The latter configuration is known as an "automatic gain control circuit" (Japanese Patent Application No. 52-1427) filed by the inventor of the present application.
Please refer to No. 6, page 3) for details. A reference carrier wave necessary for quadrature detection is reproduced by the logic circuit 26 and the VCO 27. This playback behavior.

"Carrier regeneration circuit" (also applied for by the inventor)
Since this is detailed in Japanese Patent Application No. 56-15775, the explanation will be omitted.

FIG. 6 shows another embodiment in which the present invention is applied to a 64 QAM demodulator. In this diagram, 2
8 is a carrier asynchronous detection circuit, and 34 is a logic circuit.

Other elements are the same as the embodiment shown in FIG. In this example, the control signal of the automatic gain control circuit is switched depending on whether the 64 QAM demodulator is in a steady state or a transient state. First, is the 64 QAM demodulator in a steady state?

It is determined whether the carrier synchronization circuit is in a synchronous state or an asynchronous state to determine whether the state is in a transient state. The configuration uses conventional control signals. The advantage of such a configuration is that all signals are used as control signals in a steady state where no pseudo-entrainment phenomenon occurs, so that conventional control signals with good jitter characteristics can be used. As described above, the two signal points that can be used as control signals according to the present invention are effective in preventing problems from occurring in the shear jitter characteristics, which are small as the number of multilevel values increases. Carrier asynchronous detection circuit 2
For example, the configuration of 8 may include a detector that utilizes the property that the loop impedance of the carrier synchronization circuit is high when it is asynchronous and low when it is synchronous.

FIG. 7 shows a specific example of the logic circuit 34 in the embodiment of FIG. 6, where 29 is an EX-OR circuit, and 30
31 are AND circuits, and 32 to 33 are OR circuits. In the figure, the output of EX-OR circuit 29 is a conventional control signal, and the output of flip-flop circuit 10 is a control signal according to the present invention. In the embodiment shown in FIG. 6, when the demodulator is in a transient state, the output states of P and Q are in the ranges 1 to 1 in FIG. 3, the automatic gain control signal b5 is output.

It is also possible to output the control signal b5 only when the respective output states of PtQ enter regions 1 to 3 at the same time. In the latter configuration, even when the demodulator is in a transient state.

Under the same conditions as the steady state, the corresponding signal (di, d4゜d5.d
8) can be identified and reproduced, it is possible to improve the pull-in characteristic in a transient state.

However, in the embodiments shown in FIGS. 1 and 5 above, 8
Although the explanation has been given using a pace-of-value signal as an example, it goes without saying that the present invention is not limited to this and can be applied to baseband signals of two or more values.

〔Effect of the invention〕

As is clear from the above explanation, two things according to the present invention are capable of eliminating the occurrence of pseudo-pulling-in phenomena, performing stable pulling-in operation, and being applicable to baseband signals of two or more values. Of course, 16 in microwave digital transmission
It can also be applied to value-orthogonal amplitude modulation methods, and has great effects in improving the reliability of these systems.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention;
FIG. 2 is a block diagram showing a configuration example of a conventional automatic gain control circuit, FIG. 3 is a diagram for explaining the operation of FIGS. 1 and 2, and FIG. 4 is an example of the embodiment of FIG. 1. FIG. 5 is a diagram showing a specific configuration example of the selection circuit in 6,s QA
FIG. 6 is a block diagram showing the configuration of an embodiment when the present invention is applied to an M demodulator, and FIG. FIG. 7 is a diagram showing a specific example of the configuration of the logic circuit 34 in the embodiment of FIG. 6. In the figure, 1.19 is a variable attenuator, 2.23°24 is a 4-bit A-D converter, 3.29 is an EX-OR circuit, and 4
, 5 is a low-pass filter, 6 is a logic circuit (4), 7 is a logic circuit (B), 8 and 9 are selection circuits, 10.11 is a flip-flop circuit, 12 to 15 are OR/NOR times, 16
,1■Ku↓Nimu Ishi Risa, □,. Circuit ・18, 21.22 is a subtracter, 20 is a quadrature detector,
25 is an adder, 26.34 is a logic circuit. 27 is a voltage controlled oscillator, and 28 is a carrier asynchronous detection circuit. Figure 1

Claims (1)

[Claims] 1. In an automatic gain control circuit that sets the input level of a multi-value discriminator to an optimal level in order to perform multi-value discrimination of a multi-value baseband signal, the circuit is inserted at the input side of the multi-value discriminator,
An IF band or baseband variable attenuator that changes the input level of the multi-level discriminator, and a variable attenuator that receives the output of the multi-level discriminator and determines the outermost point and the innermost point with respect to the demodulated signal. a means for determining a first region to a third region set to include the first region, and a means for performing a logical operation on the output of the determining means or the output of the determining means including the multi-value discriminator; and logic means for generating a control signal for controlling the automatic gain control circuit.