JPS6234413A - ジヨセフソンマスタ−フリツプフロツプ - Google Patents

ジヨセフソンマスタ−フリツプフロツプ

Info

Publication number
JPS6234413A
JPS6234413A JP60172517A JP17251785A JPS6234413A JP S6234413 A JPS6234413 A JP S6234413A JP 60172517 A JP60172517 A JP 60172517A JP 17251785 A JP17251785 A JP 17251785A JP S6234413 A JPS6234413 A JP S6234413A
Authority
JP
Japan
Prior art keywords
write
gate
flop
josephson
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60172517A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0428172B2 (enrdf_load_html_response
Inventor
Yuji Hatano
雄治 波多野
Hideaki Nakane
中根 英章
Kunio Yamashita
山下 邦男
Yutaka Harada
豊 原田
Ushio Kawabe
川辺 潮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP60172517A priority Critical patent/JPS6234413A/ja
Publication of JPS6234413A publication Critical patent/JPS6234413A/ja
Publication of JPH0428172B2 publication Critical patent/JPH0428172B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
JP60172517A 1985-08-07 1985-08-07 ジヨセフソンマスタ−フリツプフロツプ Granted JPS6234413A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60172517A JPS6234413A (ja) 1985-08-07 1985-08-07 ジヨセフソンマスタ−フリツプフロツプ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60172517A JPS6234413A (ja) 1985-08-07 1985-08-07 ジヨセフソンマスタ−フリツプフロツプ

Publications (2)

Publication Number Publication Date
JPS6234413A true JPS6234413A (ja) 1987-02-14
JPH0428172B2 JPH0428172B2 (enrdf_load_html_response) 1992-05-13

Family

ID=15943420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60172517A Granted JPS6234413A (ja) 1985-08-07 1985-08-07 ジヨセフソンマスタ−フリツプフロツプ

Country Status (1)

Country Link
JP (1) JPS6234413A (enrdf_load_html_response)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7247408B2 (en) 1999-11-23 2007-07-24 Sion Power Corporation Lithium anodes for electrochemical cells
US7771870B2 (en) 2006-03-22 2010-08-10 Sion Power Corporation Electrode protection in both aqueous and non-aqueous electrochemical cells, including rechargeable lithium batteries
WO2012174393A1 (en) 2011-06-17 2012-12-20 Sion Power Corporation Plating technique for electrode
US8936870B2 (en) 2011-10-13 2015-01-20 Sion Power Corporation Electrode structure and method for making the same
WO2014071160A1 (en) 2012-11-02 2014-05-08 Sion Power Corporation Electrode active surface pretreatment
JP7049269B2 (ja) 2016-05-20 2022-04-06 シオン・パワー・コーポレーション 電極用保護層および電気化学電池

Also Published As

Publication number Publication date
JPH0428172B2 (enrdf_load_html_response) 1992-05-13

Similar Documents

Publication Publication Date Title
Jain et al. Test generation for MOS circuits using D-algorithm
Lu et al. A novel CMOS implementation of double-edge-triggered flip-flops
JPS6234413A (ja) ジヨセフソンマスタ−フリツプフロツプ
CA1241388A (en) Dynamically selectable polarity latch
Lu et al. High level fault modeling of asynchronous circuits
Shadfar et al. Using VHDL Critical Path Tracing Models for Pseudo Random Test Generation
JP4495332B2 (ja) ドライバ制御信号生成回路・ic試験装置
JPH0627774B2 (ja) 故障シミュレーション方法
JPS62219300A (ja) 半導体集積回路
JPH04586Y2 (enrdf_load_html_response)
Nakanishi et al. Josephson single-input self-gating and circuits
Avhad et al. Auxiliary State Machine Controlled Autonomous Design Verification Framework
JPH03134577A (ja) テスト容易化回路
JPH10301983A (ja) 消費電力計算方法
JPH01265608A (ja) フリップフロップ回路
Ho Improved logic model for thyristor
Eggersglüß et al. A Two-Stage SAT-based ATPG Approach with Reduced Switching Activity
JPS63209319A (ja) ジヨセフソンマスタ−スレ−ブフリツプフロツプ
Varma Compiled code dynamic worst case timing simulation tracking multiple causality
JPH0215898B2 (enrdf_load_html_response)
JP2001167141A (ja) 故障シミュレータおよび故障シミュレーション方法
JPS59117818A (ja) タイミング信号発生回路
Kinsman et al. MLS, a magnetic logic simulator for magnetic bubble logic design
Sharma et al. CEERI, Pilani-333 031
JPH0544203B2 (enrdf_load_html_response)

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term