JPS6234413A - ジヨセフソンマスタ−フリツプフロツプ - Google Patents
ジヨセフソンマスタ−フリツプフロツプInfo
- Publication number
- JPS6234413A JPS6234413A JP60172517A JP17251785A JPS6234413A JP S6234413 A JPS6234413 A JP S6234413A JP 60172517 A JP60172517 A JP 60172517A JP 17251785 A JP17251785 A JP 17251785A JP S6234413 A JPS6234413 A JP S6234413A
- Authority
- JP
- Japan
- Prior art keywords
- write
- gate
- flop
- josephson
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 9
- 238000010168 coupling process Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000013016 damping Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000002085 persistent effect Effects 0.000 description 2
- 241000272470 Circus Species 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60172517A JPS6234413A (ja) | 1985-08-07 | 1985-08-07 | ジヨセフソンマスタ−フリツプフロツプ |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60172517A JPS6234413A (ja) | 1985-08-07 | 1985-08-07 | ジヨセフソンマスタ−フリツプフロツプ |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6234413A true JPS6234413A (ja) | 1987-02-14 |
JPH0428172B2 JPH0428172B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1992-05-13 |
Family
ID=15943420
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60172517A Granted JPS6234413A (ja) | 1985-08-07 | 1985-08-07 | ジヨセフソンマスタ−フリツプフロツプ |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6234413A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7247408B2 (en) | 1999-11-23 | 2007-07-24 | Sion Power Corporation | Lithium anodes for electrochemical cells |
US20070221265A1 (en) | 2006-03-22 | 2007-09-27 | Sion Power Corporation | Rechargeable lithium/water, lithium/air batteries |
JP6228915B2 (ja) | 2011-06-17 | 2017-11-08 | シオン・パワー・コーポレーション | 電極用プレーティング技術 |
EP2766949B1 (en) | 2011-10-13 | 2018-12-19 | Sion Power Corporation | Electrode structure and method for making the same |
US9005311B2 (en) | 2012-11-02 | 2015-04-14 | Sion Power Corporation | Electrode active surface pretreatment |
CN109155441B (zh) | 2016-05-20 | 2022-11-01 | 锡安能量公司 | 用于电极和电化学电池的保护层 |
-
1985
- 1985-08-07 JP JP60172517A patent/JPS6234413A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0428172B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1992-05-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Jain et al. | Test generation for MOS circuits using D-algorithm | |
Lu et al. | A novel CMOS implementation of double-edge-triggered flip-flops | |
JPS6234413A (ja) | ジヨセフソンマスタ−フリツプフロツプ | |
US20040153915A1 (en) | Resetting latch circuits within a functional circuit and a test wrapper circuit | |
CA1241388A (en) | Dynamically selectable polarity latch | |
JPS58108830A (ja) | ジヨセフソン論理集積回路 | |
Lu et al. | High level fault modeling of asynchronous circuits | |
Shadfar et al. | Using VHDL Critical Path Tracing Models for Pseudo Random Test Generation | |
TWI476616B (zh) | Estimation Method and Device of Initial Value for Simulation of DC Working Point | |
JP4495332B2 (ja) | ドライバ制御信号生成回路・ic試験装置 | |
JPH0627774B2 (ja) | 故障シミュレーション方法 | |
JPS62219300A (ja) | 半導体集積回路 | |
Nakanishi et al. | Josephson single-input self-gating and circuits | |
Avhad et al. | Auxiliary State Machine Controlled Autonomous Design Verification Framework | |
JPH03134577A (ja) | テスト容易化回路 | |
JPH10301983A (ja) | 消費電力計算方法 | |
JPH01265608A (ja) | フリップフロップ回路 | |
JPS63209319A (ja) | ジヨセフソンマスタ−スレ−ブフリツプフロツプ | |
Varma | Compiled code dynamic worst case timing simulation tracking multiple causality | |
Tjarnstrom | Clock independent timing verification of level-sensitive latches | |
Putzolu et al. | Yorktown Heights, New York | |
Kinsman et al. | MLS, a magnetic logic simulator for magnetic bubble logic design | |
Yim et al. | Simulator for path-delay faults on mixed-level circuits | |
Sharma et al. | CEERI, Pilani-333 031 | |
JPH0544203B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |