JPS6234120B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is applied to an automatic program control device that controls program switching at a broadcasting station or the like. In particular, it relates to a time counter that provides hour, minute, and second information based on the standard second pulse and a delayed pulse that is delayed by a required time from the standard second pulse.

For example, when a broadcasting station switches its own program to a program sent from far away via a relay line, there is a delay in the switching signal, so the actual switching must be delayed, and the delay pulse described above is delayed. It becomes necessary.

[Conventional technology]

A conventional circuit for this purpose is constructed as shown in FIG. That is, a second counter B that counts the standard second pulse A, a delayed multi C that generates a pulse delayed by the required time from the standard second pulse A, and a CR time constant circuit D that determines the delay time of the delayed multi C. and an AND gate E which is opened by an asynchronous set signal b given from the automatic program control device F and allows the output pulse of the delayed multi C to pass therethrough. Standard second pulse A is a reference second pulse signal, for example, broadcasting Japan Standard Time by radio wave.
This is a signal obtained by receiving and demodulating the JJY signal. Information on hours, minutes, and seconds is obtained from the output signal a of counter B. In addition, when automatic program control device F or a pulse delayed by a certain time (within 1 second) than standard pulse A is required (referred to as an asynchronous second pulse),
The AND gate E is opened by the asynchronous set signal b, and the output pulse of the delayed multi C is passed through to obtain the asynchronous second pulse c.

[Problem that the invention seeks to solve]

In the conventional circuit described above, when a plurality of types of asynchronous second pulses are required, it is necessary to provide the above-mentioned delayed multi C, CR time constant circuit D, AND gate E, etc. for each type. Further, the delay time determined by the CR time constant circuit D has a limit in its accuracy, and there is a drawback that the accuracy of the asynchronous second pulse is low. Furthermore, due to a delay in the asynchronous set signal b, the correct asynchronous second pulse may not necessarily be output. For example, an asynchronous second pulse delayed by one second may be output.

The purpose of the present invention is to solve the above-mentioned conventional drawbacks and
The object of the present invention is to provide a time counter capable of outputting an asynchronous second pulse with sufficient accuracy.

[Means for solving problems]

The time counter of the present invention is equipped with a second counter that operates at the timing of the standard second pulse, and a delay means that generates a pulse delayed by the required time from the standard second pulse, and outputs hour, minute, and second information, and automatically In a time counter that outputs an asynchronous second pulse from the delay means in response to control of a program control device, the delay means includes an internal pulse oscillator, a clock counter that counts output pulses of the internal pulse oscillator, and A memory device that sets the output value of the clock counter or its correction value or a predetermined value by an asynchronous set signal from an automatic program control device, and compares the output value of this memory device with the output value of the clock counter. and a collation device to
It is characterized in that the delay means is configured by these.

The apparatus further includes a subtraction memory for correcting the output delay time of the asynchronous set signal from the automatic program control apparatus, and a subtracter for subtracting the output value of the subtraction memory from the output of the clock counter. If the delay of the set signal is corrected,
Asynchronous second pulses can be obtained with the correct phase difference regardless of the command timing.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention. That is, the output pulses of the internal pulse oscillator 1 are counted by the clock counter 2. Clock counter 2 is reset by standard second pulse A. Then, every time the clock counter 2 outputs "0", the second counter B counts by one, and the hour, minute, and second information a is supplied to the automatic program control device F. On the other hand, the subtracter 3 subtracts the output value of the subtraction memory 6 from the output value of the clock counter 2. The memory device 4 is
The output value of the subtracter 3 is stored in accordance with the asynchronous set signal b given from the automatic program control device 8 and sent to the collation unit 5. Collator 5 compares the output value of clock counter 2 and the output value of memory 4, and when they match, outputs an asynchronous second pulse c and sends it to automatic program control device F. In the subtraction memory 6, a necessary correction amount d is preset, for example, for the delay time from the time when the asynchronous request signal 7 given to the automatic program control device 7 is input until the set signal b is output. Ru. In this embodiment, the internal pulse oscillator 1, clock counter 2, subtracter 3, memory 4, collation unit 5, subtraction memory 6, etc. constitute a delay means for generating a pulse delayed by the required time from the standard second pulse. are doing. Further, it is also possible to store an arbitrary constant value in the memory device 4 in advance.

Next, an example of the operation of this embodiment will be described. It is now assumed that the automatic program control device F is scheduled to output the control output signal 8 exactly three seconds after the moment when the asynchronous request signal 7 is applied.

Here, the asynchronous request signal 7 is the automatic program control device F.
In response to various switching control request signals,
The automatic program control device sends control outputs to various devices connected to the automatic program control device in response to this request signal.

Furthermore, the delay time from when the asynchronous request signal 7 is given to when the asynchronous set signal b is output varies depending on the difference in processing time within the automatic program control device performed in accordance with various switching controls, and the delay time is This delay time is stored as data in the control device F in advance, and after being output to the subtraction memory 6 as a correction value d, the asynchronous set signal b is output.
Output. The above correction value d of course also includes the time required to output the correction value d. The subtraction memory 6 stores the correction value d and continues to output it to the subtractor 3. The subtracter 3 subtracts the output value of the subtraction memory 6 for each output of the clock counter 2 and continues to supply the result to the memory 4. The memory 4 stores the output value of the subtracter 3 when the asynchronous set signal b is applied from the control device F. That is, memory device 4
The content of is equal to the count value of the clock counter 2 at the moment when the asynchronous request signal 7 is applied. In other words, we are remembering past timing that has passed.

Therefore, the data from the memory 4 is sent to the collation unit 5.
, the data from counter 2 has already progressed, so the asynchronous second pulse c is not output. The counter 2 continues counting, is reset by the input of the next standard second pulse A, and the count value increases again. Exactly one second after the asynchronous request signal 7 is applied, the contents of the counter 2 and the contents of the memory 4 match, and the asynchronous second pulse c is outputted from the verifier 5. Since a match from the collator 5 is obtained every second, the asynchronous second pulse c is also output every second. Control device F
can count the asynchronous second pulse c and output the control output signal 8 by the third asynchronous second pulse. The control output signal 8 is output exactly 3 seconds after the asynchronous request signal 7 is applied. Thereafter, the memory 4 is reset by the reset signal e.

When there are multiple asynchronous request signals 7 corresponding to various switching controls, the delay time until the asynchronous set signal b is output changes depending on the internal processing route of the automatic program control device F as described above. , a plurality of correction values d are prepared according to respective requests.

In addition, it is also possible to obtain an asynchronous second pulse delayed by, for example, 0.1 seconds or 0.2 seconds from the standard second pulse A by giving data to the memory device 4, for example, from the control device F, or by storing a certain value in advance. It is. In this case, subtractor 3,
The subtraction memory 6 is not required.

Furthermore, when the asynchronous second pulse is not required, the hour, minute, and second information can of course be obtained from the output value of the second counter B.

When a plurality of asynchronous second pulses are required, it is sufficient to provide only a plurality of the above-mentioned memory devices. Either a fixed value is stored in the memory in advance, a value given from the automatic program controller, or the same value as the content of the clock counter at the time the asynchronous request signal is given. It is possible to do so.

Since the delay time from when the asynchronous request signal is given to when the asynchronous set signal is output is corrected and set in the memory, an asynchronous second pulse with the correct phase difference can be output regardless of the timing at which the command is issued. I can do it. Note that the internal pulse oscillator can easily obtain sufficient accuracy.

〔Effect of the invention〕

As described above, in the present invention, the time between standard second pulses is counted by counting the output pulses of the internal pulse oscillator with a clock counter, and the output value of the clock counter matches the contents of the memory. Since the device is configured to output an asynchronous second pulse at times, it is possible to output an accurate asynchronous second pulse by appropriately setting the contents of the memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional time counter. FIG. 2 is a block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Internal pulse oscillator, 2...Clock counter, 3...Subtractor, 4...Memory, 5...Verifier, 6...Subtraction memory, 7...Asynchronous request signal,
8...Control output signal, A...Standard second pulse, B...
...Seconds counter, C...Day raid multi, D...
CR time constant circuit, E...AND gate, F...Automatic program control device, a...Hour, minute, and second information, b...Asynchronous set signal, c...Asynchronous second pulse, d...
Correction amount, e...Reset signal.

Claims (1)

[Claims] 1. A second counter that counts at the timing of a standard second pulse, and a delay means that generates a pulse delayed by a required time from the standard second pulse, and outputs hour, minute, and second information, and automatically In a time counter that outputs an asynchronous second pulse from the delay means in response to control of a program control device, the delay means includes an internal pulse oscillator and counts output pulses of the internal pulse oscillator and resets the count with the standard second pulse. a clock counter for subtracting a correction amount designated by the automatic program control device from the count value output from the clock counter; A memory device stores data at the timing of an asynchronous set signal from the device, and compares the count value output from the memory device with the count value output from the clock counter, and when the two count values become equal, the asynchronous A time counting board characterized by comprising a verifier that outputs a second pulse.