JPS6233754B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a shot barrier gate field effect transistor (hereinafter referred to as SBFET).

By using n-type gallium arsenide with a gate length of 1 μm, the SBFET has a maximum oscillation frequency of max.
40GHz is obtained. The max is determined by the gate length and parasitic resistance and capacitance. Among the parasitic factors, input loss due to gate electrode wiring resistance and source. Feedback loss due to series resistance between gate electrodes
The contribution to the decrease in max is also large. When the gate length is shortened, the wiring resistance of the gate electrode increases, and the effect of shortening the gate length cannot be fully exhibited. Also sauce. The series resistance between the gate electrodes is limited to the source due to the limits of photolithographic precision. It is difficult to shorten the distance between gates. In addition, when using SBFET in integrated circuits, in order to reduce power consumption, an enhancement type SBFET is used where no drain current flows at zero gate voltage.
SBFET or SBFET with low pinch-off voltage is promising, but the active layer thickness is as thin as ~0.1 μm, and when GaAs is used as the substrate, the source is weak due to the surface depletion layer. The thickness of the active layer between the gates becomes effectively thinner, and the thickness of the active layer between the gates becomes thinner. It becomes difficult to reduce the series resistance between the gates, and when used as a logic integrated circuit element, it becomes difficult to shorten the gate delay time.

The object of the present invention is to provide a novel method for manufacturing a short barrier gate type field effect transistor that eliminates the above-mentioned drawbacks. The present invention is a method in which a gate electrode can be formed by self-alignment, and the resistance of the gate electrode can be reduced. This is a novel method that can also reduce resistance between gates.

The invention will now be described with reference to the illustrated embodiments. 1 to 8 are schematic diagrams of manufacturing steps showing an embodiment of the present invention. "FIG. 1" shows the formation of an n-type semiconductor layer 12 having a desired impurity concentration on semi-insulating GaAs 11. A second step is performed in which a silicon nitride film (Si ₃ N ₄ ) 13 with a thickness of 3000 Å and a silicon oxide film (SiO ₂ ) 14 with a thickness of 4000 Å are formed on the surface of the n-type semiconductor layer 12.
figure". An insulating film is formed on the umbrella structure 15 using a photolithography method. The umbrella-shaped structure 15 includes an umbrella part 14' formed by etching the SiO ₂ film 14 with a hydrofluoric acid (HF)-based etchant, and an umbrella part 14' formed by etching the Si ₃ N ₄ film 13 with Freon gas (CF ₄ ) using the umbrella part 14' as a mask. and an eave portion 13' formed by plasma etching. Eave part 1
3' can be easily formed by setting the plasma etching output and etching time. In the example, the length of the umbrella part 14' is 2.0 μm, and the length of the eave part 13' is
It was set to 0.7 μm. Using the eaves part 13 and the umbrella part 14' of the umbrella-like structure 15 as a mask, Si is implanted using an ion implantation method.
"Figure 3" shows ion implantation of ion 16 at 5X10 ¹³ cm ^-2 at 150 KeV. "FIG. 4" shows that a high concentration n-type semiconductor layer 17 is formed by heat treatment at 850° C. for 30 minutes in an arsenic atmosphere gas. The high concentration n-type semiconductor layer 17 is located at the eaves portion 13'.
It is important that the n-type semiconductor layer 12 in contact with the n-type semiconductor layer 12 is not converted into the high concentration n-type semiconductor layer 17. Therefore, it is necessary to select the length of the umbrella part 14' and the eave part 13', ion implantation conditions, and heat treatment conditions. The n-type semiconductor layer 12 in contact with the eaves portion 13' is replaced with a high concentration n-type semiconductor layer 17.
When converted to , gate breakdown voltage decreases and pinch-off voltage becomes difficult to control. Using the umbrella-shaped structure 15 as a mask, a metal made of gold-germanium (Au-Ge) is deposited to a thickness of 1200 Å using a vacuum evaporation method, and heat-treated to form a source electrode 18 and a drain electrode 19.
figure". The source electrode 18 and drain electrode 19 were formed by a self-alignment method using the umbrella structure 15 as a mask, but since the high concentration n-type semiconductor layer 17 was formed by a self-alignment method, the source electrode 18 and drain electrode 19 were formed by a self-alignment method using the umbrella-shaped structure 15 as a mask. The inter-gate resistance can be sufficiently reduced, and the source electrode 18 and drain electrode 19 may be formed using photolithography. A metal film is also formed on the surface of the umbrella portion 14', but this does not pose a problem. An organic compound 20 such as a photosensitive resin is applied to the entire surface using a spinner or the like. In this case, the coating is applied thickly to the concave portions and thinly to the convex portions. "FIG. 6" shows that this is exposed to oxygen plasma to etch the organic compound and expose the surface of the umbrella portion 14'. The organic compound 20 is formed at the eave portion 13' as shown in FIG. "FIG. 7" shows that the umbrella-shaped structure 15 is removed and a metal layer 21 that will become a shot electrode is deposited by vacuum evaporation. For example, alkynium (Al) or the like is used as the shot electrode. By removing the organic compound 20, the metal on the organic compound 20 is also removed using a so-called list-off method.
``Figure 8'' forming 1'. Shock electrode 21'
becomes an umbrella-shaped electrode layer as shown in FIG. 8, and the gate length can be shortened and gate resistance can be reduced. To form the gate electrode using the lift-off method,
The thickness of the metal 21 is preferably thinner than the thickness of the umbrella-shaped structure 15. If the thickness of the metal 21 is thicker than the thickness of the umbrella-shaped structure 15, an organic compound such as a photosensitive resin is buried in the recess as shown in FIG. 7, and the metal on the organic compound 20 is removed by etching or the like. After that, the organic compound 20 may be removed.

Although the above embodiments have been explained using GaAs, it goes without saying that the present invention can be applied to SBFETs using other semiconductor materials, such as silicon, indium, arsenic-phosphorus mixtures, and the like.

As explained in the embodiments above, the present invention provides the first
After forming an umbrella-like structure consisting of an insulating layer and a second insulating layer, and filling the eaves with an organic compound of photosensitive resin, the first and second insulating layers are removed and the umbrella is used as a shot electrode. Since the umbrella-shaped metal layer is formed, the gate length is determined by the umbrella-shaped metal layer in contact with the semiconductor substrate surface, and the gate length can be easily shortened by shortening the length of the first insulating layer. Furthermore, the wiring resistance of the gate electrode can be reduced despite the short gate length due to the umbrella-shaped metal layer. And the sauce. The series resistance between the gate electrodes is also determined by forming a highly doped n-type semiconductor layer by ion implantation, using the umbrella-shaped structure consisting of the first insulating layer and the second insulating layer as a mask, and forming the source. Source by self-alignment method by forming drain electrode. Since the drain region is formed, the gate. The distance between the sources can be shortened, and the series resistance between the source and gate electrodes can be reduced. Furthermore, gate resistance and source. The series resistance between gates can be reduced, the maximum oscillation frequency of the SBFET can be improved, and if the SBFET manufactured by the method of the present invention is used in an integrated circuit, propagation delay time and power consumption can be reduced.

[Brief explanation of the drawing]

1 to 8 show GaAs according to the present invention.
FIG. 2 is a schematic diagram of a manufacturing process for explaining an example of a method for manufacturing an SBFET. 11 is semi-insulating GaAs, 12 is an n-type semiconductor layer,
13 is a silicon nitride film, 14 is a silicon oxide film,
15 is an umbrella-shaped structure, 16 is a Si ion, 17 is a high concentration n-type semiconductor layer, 18 is a source electrode, 19 is a drain electrode, 20 is an organic compound, and 21 is a metal layer.

Claims (1)

[Scope of Claims] 1. A step of forming an umbrella-like structure consisting of a first insulating layer and a second insulating layer on the surface of the semiconductor substrate, and forming an organic compound on the surface of the semiconductor substrate with approximately the same height as the umbrella-like structure. a step of forming a layer and also filling the eaves of the umbrella-like structure with an organic compound, a step of removing the first and second insulating layers and forming a metal layer, removing the organic compound and A method for manufacturing a semiconductor device comprising the steps of removing a metal layer on an organic compound and forming an umbrella-shaped metal layer. 2. a first insulating layer formed on the surface of the semiconductor substrate;
2. The method of manufacturing a semiconductor device according to claim 1, wherein the source and drain regions are formed on the semiconductor substrate using an umbrella-shaped structure made of the second insulating layer as a mask.