JPS6233673B2 - - Google Patents

Info

Publication number
JPS6233673B2
JPS6233673B2 JP55013307A JP1330780A JPS6233673B2 JP S6233673 B2 JPS6233673 B2 JP S6233673B2 JP 55013307 A JP55013307 A JP 55013307A JP 1330780 A JP1330780 A JP 1330780A JP S6233673 B2 JPS6233673 B2 JP S6233673B2
Authority
JP
Japan
Prior art keywords
node
mos transistor
level
control signal
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55013307A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56111183A (en
Inventor
Isao Ogura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP1330780A priority Critical patent/JPS56111183A/ja
Publication of JPS56111183A publication Critical patent/JPS56111183A/ja
Publication of JPS6233673B2 publication Critical patent/JPS6233673B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
JP1330780A 1980-02-06 1980-02-06 Mos integrated circuit device Granted JPS56111183A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1330780A JPS56111183A (en) 1980-02-06 1980-02-06 Mos integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1330780A JPS56111183A (en) 1980-02-06 1980-02-06 Mos integrated circuit device

Publications (2)

Publication Number Publication Date
JPS56111183A JPS56111183A (en) 1981-09-02
JPS6233673B2 true JPS6233673B2 (enrdf_load_stackoverflow) 1987-07-22

Family

ID=11829515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1330780A Granted JPS56111183A (en) 1980-02-06 1980-02-06 Mos integrated circuit device

Country Status (1)

Country Link
JP (1) JPS56111183A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0689712A4 (en) * 1993-03-17 1997-05-28 Zycad Corp CONFIGURABLE FIELDS WITH DIRECT ACCESS MEMORY ARRANGEMENT

Also Published As

Publication number Publication date
JPS56111183A (en) 1981-09-02

Similar Documents

Publication Publication Date Title
US5973552A (en) Power savings technique in solid state integrated circuits
CA2000995C (en) Wordline voltage boosting circuits for complementary mosfet dynamic memories
JP3286869B2 (ja) 内部電源電位発生回路
JPH0427731B2 (enrdf_load_stackoverflow)
US5757714A (en) Semiconductor memory device with on-chip boosted power supply voltage generator
EP0052504B1 (en) Semiconductor buffer circuit
US5369320A (en) Bootstrapped high-speed output buffer
US5631867A (en) Semiconductor storage device requiring short time for program voltage to rise
US4239991A (en) Clock voltage generator for semiconductor memory
IE50579B1 (en) Bootstrap circuit
US5134317A (en) Booster circuit for a semiconductor memory device
US4352996A (en) IGFET Clock generator circuit employing MOS boatstrap capacitive drive
US6147923A (en) Voltage boosting circuit
US7084684B2 (en) Delay stage insensitive to operating voltage and delay circuit including the same
US4468576A (en) Inverter circuit having transistors operable in a shallow saturation region for avoiding fluctuation of electrical characteristics
JPS6233673B2 (enrdf_load_stackoverflow)
JPH03283182A (ja) 半導体昇圧回路
JPH0758887B2 (ja) Ｒｃ時定数を利用した可変クロック遅延回路
US4746824A (en) High potential hold circuit
EP0109004B1 (en) Low power clock generator
KR100432985B1 (ko) 상승된출력전압을발생시키기위한회로
US5907257A (en) Generation of signals from other signals that take time to develop on power-up
JP3890614B2 (ja) 昇圧電圧供給回路
JPH0323591A (ja) 半導体回路
JP2672023B2 (ja) 基板電圧発生回路