JPS6232619B2 - - Google Patents
Info
- Publication number
- JPS6232619B2 JPS6232619B2 JP54154370A JP15437079A JPS6232619B2 JP S6232619 B2 JPS6232619 B2 JP S6232619B2 JP 54154370 A JP54154370 A JP 54154370A JP 15437079 A JP15437079 A JP 15437079A JP S6232619 B2 JPS6232619 B2 JP S6232619B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- semiconductor region
- forming
- electrode
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 37
- 239000004020 conductor Substances 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 238000007747 plating Methods 0.000 claims description 9
- 238000009713 electroplating Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 239000012535 impurity Substances 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 238000005530 etching Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 230000016507 interphase Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- -1 Cr and Ti Chemical class 0.000 description 1
- 229910001252 Pd alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
(1) 発明の利用分野
本発明は半導体装置の電極形成法、特にDHD
（ダブルヒートシンクダイオード）型のダイオー
ドにおける電極を形成する方法に関する。[Detailed Description of the Invention] (1) Field of Application of the Invention The present invention relates to a method for forming electrodes of semiconductor devices, particularly DHD.
The present invention relates to a method of forming an electrode in a (double heat sink diode) type diode.
(2) 従来技術及びその問題点
従来、Ｐ型基板を使用したシヨツトキーダイオ
ードの場合、メツキ時に接合が逆バイアスとなり
電流が流れず不可能であるため、第１図に示すよ
うにバリアメタルであるCr―Ag層３をウエハー
１全面に残したままでホトレジスト４によりメツ
キ径をしぼつてAgバンプ電極５を電気メツキ形
成している。しかる後、レジスト除去し、Agバ
ンプ電極５をマスクとしてCr―Ag層３のエツチ
をしている。(2) Prior art and its problems Conventionally, in the case of a Schottky diode using a P-type substrate, the junction becomes reverse biased during plating, making it impossible for current to flow. While leaving the Cr--Ag layer 3 on the entire surface of the wafer 1, the plating diameter is reduced using photoresist 4, and Ag bump electrodes 5 are formed by electroplating. Thereafter, the resist is removed and the Cr--Ag layer 3 is etched using the Ag bump electrode 5 as a mask.
このCr―Ag層３のエツチの際にAgバンプ電極
５も若干エツチされたり、電極５直下のホトレジ
スト４が完全に除去されないためにCr―Ag層３
がエツチされなかつたりした。このため、Cr―
Ag層３のエツチ時の電極径のばらつきにより容
量がばらつくという欠点が生じた。また電極材料
としてCr、Ti等酸化膜と密着のよい一部の金属
しか使えないという制約が生じて材料選択の自由
度が損なわれていた。 During etching of the Cr--Ag layer 3, the Ag bump electrode 5 may also be slightly etched, and the photoresist 4 directly under the electrode 5 may not be completely removed.
was not fucked, but it was leaking. For this reason, Cr—
A drawback occurred in that the capacitance varied due to variations in the electrode diameter when the Ag layer 3 was etched. Furthermore, there was a restriction that only certain metals such as Cr and Ti, which have good adhesion to the oxide film, could be used as electrode materials, reducing the degree of freedom in material selection.
なお、第１図において、ｉはメツキ電流、２は
SiO2膜、６はAg板を示す。 In addition, in Fig. 1, i is the plating current, and 2 is the plating current.
SiO 2 film, 6 indicates Ag plate.
(3) 発明の目的
電気メツキ用の導体層のエツチをホトレジ工程
により精度良く形成する事を可能にする。又、電
極材料選択の自由度を増す。(3) Purpose of the invention To enable etching of a conductor layer for electroplating to be formed with high accuracy by a photoresist process. Furthermore, the degree of freedom in selecting electrode materials is increased.
(4) 発明の要点
本発明によれば、Ｐ型半導体基板の一主面に形
成されたPN接合で区画されたＮ型半導体領域に
電気メツキによりバンプ電極を形成するPN接合
を有する半導体装置の電極形成法において、上記
Ｎ型半導体領域を取り囲みかつ該Ｎ型半導体領域
と離間して上記Ｐ型半導体基板の主面に高濃度の
Ｐ型ガードリング半導体領域を形成する工程と、
上記Ｎ型半導体領域上に第１の導体層を選択的に
形成する工程と、上記第１の導体層と上記ガード
リング半導体領域との間を電気的接続するため
に、上記Ｐ型半導体基板の主面に絶縁膜を介して
第２の導体層を形成する工程と、上記第１の導体
層から上記第２の導体層を通して上記ガードリン
グ半導体領域にメツキ用電流を流すことによつて
上記第１の導体層上にバンプ電極を電気メツキす
る工程と、しかる後、上記第２の導体層を除去す
る工程とより成ることを特徴とする。(4) Summary of the Invention According to the present invention, a semiconductor device having a PN junction is provided in which a bump electrode is formed by electroplating in an N-type semiconductor region defined by a PN junction formed on one main surface of a P-type semiconductor substrate. In the electrode forming method, forming a highly concentrated P-type guard ring semiconductor region on the main surface of the P-type semiconductor substrate surrounding and spaced from the N-type semiconductor region;
selectively forming a first conductor layer on the N-type semiconductor region; forming a second conductor layer on the main surface via an insulating film; and passing a plating current from the first conductor layer to the guard ring semiconductor region through the second conductor layer. The method is characterized by comprising a step of electroplating a bump electrode on the first conductor layer, and then a step of removing the second conductor layer.
(5) 発明の実施例
実施例 １
ここで説明される実施例はチヤンネル防止のた
めのガードリング領域を有するPN接合ダイオー
ドである。(5) Embodiments of the Invention Embodiment 1 The embodiment described here is a PN junction diode having a guard ring region for channel prevention.
第２図はかかるダイオードのAgバンプを形成
する状態を示した説明図である。図に示すダイオ
ードは半導体ウエーハの状態で次の工程により形
成される。 FIG. 2 is an explanatory diagram showing the state in which Ag bumps of such a diode are formed. The diode shown in the figure is formed on a semiconductor wafer through the following steps.
(a) P+型半導体基板１が準備される。(a) A P + type semiconductor substrate 1 is prepared.
(b) 基板１表面上にP-型エピタキシヤル層１０
が形成される。(b) P - type epitaxial layer 10 on the surface of the substrate 1
is formed.
(c) P-型エピタキシヤル層１０表面上にSiO2膜
のような絶縁物質膜２が形成される。(c) An insulating material film 2 such as a SiO 2 film is formed on the surface of the P - type epitaxial layer 10 .
(d) SiO2膜２をホトレジスト処理により選択的
にエツチングし、そのSiO2膜２に第１の不純
物導入用窓およびその第１の不純物導入用窓よ
り離間され、かつその窓を取り囲むリング状の
第２の不純物導入用窓を形成する。(d) The SiO 2 film 2 is selectively etched by photoresist treatment, and a first impurity introduction window and a ring shape surrounding the first impurity introduction window are formed in the SiO 2 film 2 and are separated from the first impurity introduction window. A second impurity introduction window is formed.
(e) 第２の不純物導入用窓を通してP-型エピタ
キシヤル層１０内にＰ型決定不純物、例えばボ
ロンを拡散またはイオン打込みにより導入し、
深さ約２μのP+型ガードリング半導体領域１
２を形成する。(e) introducing a P-type determining impurity, such as boron, into the P - type epitaxial layer 10 through a second impurity introduction window by diffusion or ion implantation;
P + type guard ring semiconductor region 1 with a depth of about 2μ
form 2.
(f) 第１の不純物導入用窓を通してP-型エピタ
キシヤル層１０内にｎ型決定不純物、例えばリ
ンあるいはヒ素を拡散またはイオン打込みによ
り導入し、深さ約1.5μの基板と反対導電型の
n+型半導体領域１１を形成する。(f) Introduce an n-type determining impurity, such as phosphorus or arsenic, into the P - type epitaxial layer 10 by diffusion or ion implantation through the first impurity introduction window to form a substrate of the opposite conductivity type to a depth of approximately 1.5 μm.
An n + type semiconductor region 11 is formed.
(f) n+型半導体領域１１に接続し、SiO2膜２表
面上に延在するCr―Ag層３をホトレジスト処
理により選択的に形成する。(f) A Cr—Ag layer 3 connected to the n + type semiconductor region 11 and extending on the surface of the SiO 2 film 2 is selectively formed by photoresist treatment.
(h) 基板１０全面にAlより成る導体層７を被着
する。この導体層７の厚さは10000Å程度であ
る。(h) A conductor layer 7 made of Al is deposited on the entire surface of the substrate 10. The thickness of this conductor layer 7 is approximately 10,000 Å.
(i) Cr―Ag層３が露出するようにこの導体層７
がホトレジスト４をマスクとして選択的にエツ
チされる。この導体層７の選択的エツチの際に
はCr―Ag層３はエツチされない。なぜなら
ば、導体層７のエツチングは、アルカリエツチ
液が用いられるためである。(i) Cut this conductor layer 7 so that the Cr-Ag layer 3 is exposed.
is selectively etched using the photoresist 4 as a mask. During this selective etching of conductor layer 7, Cr--Ag layer 3 is not etched. This is because the conductor layer 7 is etched using an alkaline etchant.
このようにして得られたダイオードは第２図に
示されるように電気メツキ処理が施され、Agバ
ンプ電極５が形成される。 The diode thus obtained is subjected to electroplating as shown in FIG. 2, and Ag bump electrodes 5 are formed.
このAgバンプ電極５形成の際、メツキ電流ｉ
は矢印に示されたように流れる。すなわち、メツ
キ電流ｉは、Agバンプ電極５→Cr―Ag層３→導
体層７→P+型ガードリング半導体領域１２→P-
型エピタキシヤル層１０→基板１の経路で流れ
る。このような電流経路は半導体ウエーハに構成
された各ダイオードに対して確実に実行されるの
で、極めて短時間でAgバンプ電極形成が行なわ
れる。 When forming this Ag bump electrode 5, plating current i
flows as shown by the arrow. That is, the plating current i is as follows: Ag bump electrode 5 → Cr-Ag layer 3 → conductor layer 7 → P + type guard ring semiconductor region 12 → P -
It flows along the path from the type epitaxial layer 10 to the substrate 1. Since such a current path is reliably carried out for each diode formed on the semiconductor wafer, the Ag bump electrodes can be formed in an extremely short time.
この後、ホトレジスト４および導体層７がエツ
チングされる。なお、導体層７は完全に除去せ
ず、P+型ガードリング半導体領域１２に接続さ
れ、かつSiO2膜２の表面に延在するように選択
にエツチする。エツチ液はアルカリエツチ液（例
えば、KOH20ｇ／１純水の水溶液）が使用さ
れる。この結果第３図で示す如き構造のダイオー
ドが得られる。なお、第３図から明らかなように
バンプ電極５の方向にのびる導体層７（ガードリ
ング電極）の端部はP+型ガードリング半導体領
域１２をこえて位置している。これは、寄生チヤ
ンネル（Ｎ型）がその領域１２に達しないように
するためである。このため耐圧低下の防止が計れ
る。 After this, the photoresist 4 and the conductor layer 7 are etched. Note that the conductor layer 7 is not completely removed, but is selectively etched so that it is connected to the P + type guard ring semiconductor region 12 and extends over the surface of the SiO 2 film 2. As the etch solution, an alkaline etch solution (for example, a 20 g KOH/1 aqueous solution of pure water) is used. As a result, a diode having a structure as shown in FIG. 3 is obtained. As is clear from FIG. 3, the end of the conductor layer 7 (guard ring electrode) extending in the direction of the bump electrode 5 is located beyond the P + type guard ring semiconductor region 12. This is to prevent parasitic channels (N type) from reaching the region 12. Therefore, it is possible to prevent a drop in breakdown voltage.
実施例 ２
ここで説明される実施例は前記実施例の変形例
である。すなわち、ダイオードの構造が若干前記
実施例のダイオードと異なつている。Example 2 The example described here is a modification of the previous example. That is, the structure of the diode is slightly different from the diode of the previous embodiment.
第４図にそのダイオードにおけるAgバンプ電
極形成の状態が示される。第４図に示されたダイ
オードはn+型半導体領域１１と接触する導体層
３としてTi―Pd合金が用いられている。そし
て、この導体層３と同時に形成されたガードリン
グ電極１３が設けられている。そして、さらに
CVD―SiO2膜あるいはPSG膜のような相間絶縁
膜１４を介してメツキ電流経路をつくるための
Alから成る導体層７が形成されている。この相
間絶縁膜１４は電極１３とバンプ電極５との間の
シヨート防止の役目をはたす。 FIG. 4 shows the state of Ag bump electrode formation in the diode. In the diode shown in FIG. 4, a Ti--Pd alloy is used as the conductor layer 3 in contact with the n + -type semiconductor region 11. A guard ring electrode 13 formed simultaneously with this conductor layer 3 is provided. And further
For creating a plating current path through an interphase insulating film 14 such as CVD-SiO 2 film or PSG film.
A conductor layer 7 made of Al is formed. This interphase insulating film 14 serves to prevent shorts between the electrode 13 and the bump electrode 5.
Agバンプ電極５が形成された後、導体層７お
よびホトレジスト４が完全に除去され、第５図の
ようなダイオードが得られる。導体層７のエツチ
液は前述と同様にアルカリエツチ液が使用され
る。そして、導体層７が形成された開口部１５に
そつて個々のペレツトに分割される。この場合、
P+型ガードリング半導体領域１２の形状は形成
すべきペレツトの外周形状と同一形態にされる。 After the Ag bump electrode 5 is formed, the conductor layer 7 and the photoresist 4 are completely removed, resulting in a diode as shown in FIG. As the etchant for the conductor layer 7, an alkaline etchant is used as described above. It is then divided into individual pellets along the opening 15 in which the conductor layer 7 is formed. in this case,
The shape of the P + type guard ring semiconductor region 12 is made to be the same as the outer peripheral shape of the pellet to be formed.
なお、導体層７は完全に除去せず、第３図のよ
うに表面保護として残しておいてもよい。 Note that the conductor layer 7 may not be completely removed, but may be left as a surface protection as shown in FIG.
(6) 発明の効果
発明の採用によれば、電極形状がCr―Ag層あ
るいはTi―Pd層のホトレジスト処理により精度
良く決定されるので、均一なAgバンプ電極を形
成することが可能となつた。また、導体材料の選
択の自由度が増大した。(6) Effects of the invention According to the adoption of the invention, the shape of the electrode is determined with high precision by photoresist processing of the Cr--Ag layer or the Ti--Pd layer, so it has become possible to form a uniform Ag bump electrode. . Furthermore, the degree of freedom in selecting conductor materials has increased.
なお、本発明は複数のトランジスタやダイオー
ドを有するICデバイスにも適用される。 Note that the present invention is also applicable to IC devices having multiple transistors and diodes.
第１図は従来の方法を説明する半導体装置の断
面図、第２図、第４図は本発明の方法を説明する
半導体装置の断面図、第３図および第５図は本発
明の方法によつて得られた半導体装置の断面図で
ある。
３……導体層、５……Agバンプ電極、７……
Alより成る導体層。
FIG. 1 is a cross-sectional view of a semiconductor device for explaining the conventional method, FIGS. 2 and 4 are cross-sectional views of a semiconductor device for explaining the method of the present invention, and FIGS. 3 and 5 are cross-sectional views of a semiconductor device for explaining the method of the present invention. FIG. 3 is a cross-sectional view of the semiconductor device thus obtained. 3... Conductor layer, 5... Ag bump electrode, 7...
A conductor layer made of Al.
Claims (1)
合で区画されたＮ型半導体領域に電気メツキによ
りバンプ電極を形成するPN接合を有する半導体
装置の電極形成法において、上記Ｎ型半導体領域
を取り囲みかつ該Ｎ型半導体領域と離間して上記
Ｐ型半導体基板の主面に高濃度のＰ型ガードリン
グ半導体領域を形成する工程と、上記Ｎ型半導体
領域上に第１の導体層を選択的に形成する工程
と、上記第１の導体層と上記ガードリング半導体
領域との間を電気的接続するために、上記Ｐ型半
導体基板の主面に絶縁膜を介して第２の導体層を
形成する工程と、上記第１の導体層から上記第２
の導体層を通して上記ガードリング半導体領域に
メツキ用電流を流すことによつて上記第１の導体
層上にバンプ電極を電気メツキする工程と、しか
る後、上記第２の導体層を除去する工程とより成
ることを特徴とする半導体装置の電極形成法。 ２ 上記第１の導体層を形成する工程において、
上記Ｐ型ガードリング半導体領域に電気的接続さ
れるガードリング電極を同時に形成することを特
徴とする特許請求の範囲第１項記載の半導体装置
の電極形成法。[Claims] 1. An electrode formation method for a semiconductor device having a PN junction, in which a bump electrode is formed by electroplating in an N-type semiconductor region defined by a PN junction formed on one main surface of a P-type semiconductor substrate, forming a highly doped P-type guard ring semiconductor region on the main surface of the P-type semiconductor substrate surrounding the N-type semiconductor region and spaced from the N-type semiconductor region; selectively forming a conductor layer on the main surface of the P-type semiconductor substrate via an insulating film in order to electrically connect between the first conductor layer and the guard ring semiconductor region. a step of forming a second conductor layer, and a step of forming a conductor layer from the first conductor layer to the second conductor layer;
electroplating a bump electrode on the first conductor layer by passing a plating current through the guard ring semiconductor region through the conductor layer; and then removing the second conductor layer. A method for forming an electrode for a semiconductor device, characterized by comprising the steps of: 2 In the step of forming the first conductor layer,
2. The method of forming an electrode for a semiconductor device according to claim 1, wherein a guard ring electrode electrically connected to the P-type guard ring semiconductor region is simultaneously formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15437079A JPS5678141A (en) | 1979-11-30 | 1979-11-30 | Method of forming electrode for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15437079A JPS5678141A (en) | 1979-11-30 | 1979-11-30 | Method of forming electrode for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5678141A JPS5678141A (en) | 1981-06-26 |
| JPS6232619B2 true JPS6232619B2 (en) | 1987-07-15 |
Family
ID=15582669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15437079A Granted JPS5678141A (en) | 1979-11-30 | 1979-11-30 | Method of forming electrode for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5678141A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS614248A (en) * | 1984-06-19 | 1986-01-10 | Nec Kansai Ltd | Forming method of bump electrode |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54105962A (en) * | 1978-02-07 | 1979-08-20 | Mitsubishi Electric Corp | Projection electrode forming method for semiconductor device |
-
1979
- 1979-11-30 JP JP15437079A patent/JPS5678141A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54105962A (en) * | 1978-02-07 | 1979-08-20 | Mitsubishi Electric Corp | Projection electrode forming method for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5678141A (en) | 1981-06-26 |
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