JPS614248A - Forming method of bump electrode - Google Patents

Forming method of bump electrode

Info

Publication number
JPS614248A
JPS614248A JP59125742A JP12574284A JPS614248A JP S614248 A JPS614248 A JP S614248A JP 59125742 A JP59125742 A JP 59125742A JP 12574284 A JP12574284 A JP 12574284A JP S614248 A JPS614248 A JP S614248A
Authority
JP
Japan
Prior art keywords
electrode
type semiconductor
semiconductor layer
type
bump electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59125742A
Other languages
Japanese (ja)
Inventor
Shuzo Ito
伊藤 修三
Goro Ikegami
五郎 池上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP59125742A priority Critical patent/JPS614248A/en
Publication of JPS614248A publication Critical patent/JPS614248A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To make it possible to form a homogeneous bump electrode, by forming a shorting electrode, which shorts both semiconductor layers, on the first insulating film protecting the P-N junction between the P type and N type semiconductor layers, thereafter flowing a plating current to the shorting electrode, and forming the bump electrode. CONSTITUTION:Parts of a first insulating film 6 on a P<-> type semiconductor layer 2 and an N type semiconductor layer 3 are partially removed and window holes 20 and 21 are formed. Then, on the insulating film 6 between both window holes 20 and 21, a shorting electrode 22 comprising a Ti-Ag evaporated thin film and the like is deposited and formed. Thus the N type semiconducutor layer 3 and the P type semiconductor layer 2 are shorted. The specified part of the shorting electrode on the N type semiconductor layer 3 is made to remain, and a second insulating film 23 is deposited. A negative voltage is applied to the back surface of a P<+> type semiconductor substrate 1 in Ag plating liquid. A positive voltage is applied to an Ag plate 24 in the Ag plating liquid. Then, the plating current I does not flow in an N-P junction part but flows through the P<-> semiconductor layer 2 and the P<+> type semiconductor layer 1 from the shorting electrode 22. Positive Ag ions are attached to the exposed surface of the shorting electrode 22. A bump electrode 5' is grown and formed.

Description

【発明の詳細な説明】 産1止9−札朋分1 この発明はバンプ電極の形成方法に関し、特に例えばN
型アノード、P型カソードタイプのダイオードのN型ア
ノードにバンプ電極を形成する方法に関する。
[Detailed Description of the Invention] The present invention relates to a method of forming a bump electrode, and particularly to a method for forming a bump electrode, for example, N
The present invention relates to a method for forming a bump electrode on an N-type anode of a P-type anode and a P-type cathode type diode.

l来■伎■ 定電圧ダイオードなどの一般のダイオードはP型アノー
ド、N型カソードタイプでP型アノードをAgのバンプ
電極で形成したものがほとんどである。このN型カソー
ドタイプのダイオードにおけるバンプ電極はPN接合部
の順方向にメッキ電流を流せばアノード側にAgプラス
イオンが付着して簡単に而も均一な大きさで形成できる
Most common diodes, such as constant voltage diodes, have a P-type anode and an N-type cathode, and the P-type anode is formed with an Ag bump electrode. The bump electrode in this N-type cathode type diode can be easily formed with a uniform size by applying a plating current in the forward direction of the PN junction, by depositing Ag positive ions on the anode side.

ところで、上記タイプのダイオードは温度特性の改善や
低ノイズ化に限界かあ・す、そこで温度特性やノイズ特
性を改善した高信頼度のダイオードとしてN型アノード
、P型カソードタイプのものが開発され、一部でパンチ
スルー型ダイオードとして実用化されている。このP型
カソードタイプのダイオードの基本構造を第4図に、前
記パンチスルー型ダイオードの一構造例を第5図に示し
以下順次説明する。
By the way, the above types of diodes are limited in their ability to improve temperature characteristics and reduce noise, so N-type anode and P-type cathode types have been developed as highly reliable diodes with improved temperature and noise characteristics. , some have been put into practical use as punch-through diodes. The basic structure of this P-type cathode type diode is shown in FIG. 4, and an example of the structure of the punch-through type diode is shown in FIG. 5, and will be explained in sequence below.

第4図における(1)は高不純物濃度のP+型半導体基
板、(2)はP+型半導体基板(1)上にエピタキシャ
ル成長させた低不純物濃度のP”″型半導体層、(3)
はP−型半導体N(2)の表層部にN型不純物を選択拡
散して形成したN型半導体層、(4)はP十半導体基−
@ (1’)の裏面にオーミック接触して形成された裏
面電極、(5)はN型半導体層(3)上にオーミック接
触して形成されたAgのバンプ電極、(6)はNP接合
部(7)の表面を絶縁し保護する絶縁膜である。バンプ
電極(5)はNP接合部(7)に逆電圧を印加してブレ
ークダウンさせて逆方向にメッキ電流を流し、N型半導
体層(3)上にAgプラスイオンを41着させ成長させ
て形成される。
In Fig. 4, (1) is a P+ type semiconductor substrate with a high impurity concentration, (2) is a P'' type semiconductor layer with a low impurity concentration epitaxially grown on the P+ type semiconductor substrate (1), and (3) is a P+ type semiconductor layer with a low impurity concentration.
is an N-type semiconductor layer formed by selectively diffusing N-type impurities into the surface layer of a P-type semiconductor N(2), and (4) is a P-type semiconductor base layer.
@(1') is a back electrode formed in ohmic contact with the back surface, (5) is an Ag bump electrode formed in ohmic contact on the N-type semiconductor layer (3), and (6) is an NP junction. (7) This is an insulating film that insulates and protects the surface. The bump electrode (5) is made by applying a reverse voltage to the NP junction (7) to cause it to break down, and then passing a plating current in the opposite direction to deposit and grow 41 Ag positive ions on the N-type semiconductor layer (3). It is formed.

第5vIlのバンチスルー型ダイオードはNPNトラン
ジスタのC−B間耐圧を利用したもので、(8)はN十
型半導体基板、(9)はN+型半導体基板(8)上にエ
ピタキシャル成長させたN−型半導体層、(10)はN
−型半導体層(9)の表層部に部分的に形成したP型半
導体層、(11)はP型半導体層 (10)の表層部に
部分的に形成したN型半導体層、(12)はN十型半導
体基板(8)の裏面にオーミック接触して形成された裏
面電極、(13)はN型半導体層(11)上にオーミッ
ク接触して形成されたバンプ?′!極、(14)はN−
型半導体1if(9)とP型半導体層 (10) ノP
N接合i (15) 表面上ニ形成された(9) −(
10)間を短絡する電極、(16)は絶縁膜である。バ
ンプ電極(13)はP+型半導体M (10)とN型半
導体層(11)のNP接合部(17)に逆方向電圧を印
加して逆方向のメッキ電流を流して行われる。
The bunch-through diode of the fifth vIl utilizes the C-B withstand voltage of an NPN transistor. type semiconductor layer, (10) is N
A P-type semiconductor layer partially formed on the surface layer of the −-type semiconductor layer (9), (11) an N-type semiconductor layer partially formed on the surface layer of the P-type semiconductor layer (10), and (12) The back electrode (13) is formed in ohmic contact with the back surface of the N-type semiconductor substrate (8), and the bump (13) is formed in ohmic contact on the N-type semiconductor layer (11). ′! pole, (14) is N-
type semiconductor 1if (9) and P type semiconductor layer (10) noP
N junction i (15) formed on the surface (9) −(
10) An electrode for short-circuiting between the electrodes, (16) is an insulating film. The bump electrode (13) is formed by applying a reverse voltage to the NP junction (17) between the P+ type semiconductor M (10) and the N type semiconductor layer (11) and passing a plating current in the opposite direction.

このバンチスルー型ダイオードのバンプ電極(13)に
プラス、裏面電極(12)にマイナスの電圧を加えると
NP接合部(17)よりP型半導体層(10)内へ図示
矢印の如く空乏Jit (1B)が延び、これが電極(
14)に達するとバンチスル。−を起こしてブレークダ
ウンする。この場合、P型半導体層(10)とN−型半
導体層(9)が同一電位のためP型半導体Fi! (1
0)がらN−型半導体層(9)への少数キャリアの注入
が生じず、これがため温度特性の良い低ノイズのダイオ
ードが得られる。このようなバンチスルー型ダイオード
の特徴は例えば特公昭56年30708号公報に開示さ
れている。
When a positive voltage is applied to the bump electrode (13) and a negative voltage is applied to the back electrode (12) of this bunch-through diode, the depletion Jit (1B ) extends, and this becomes the electrode (
14) When it reaches 14, it's bantisuru. - causes a breakdown. In this case, since the P type semiconductor layer (10) and the N- type semiconductor layer (9) have the same potential, the P type semiconductor Fi! (1
0), no minority carriers are injected into the N- type semiconductor layer (9), and as a result, a diode with good temperature characteristics and low noise can be obtained. The characteristics of such a bunch-through diode are disclosed in, for example, Japanese Patent Publication No. 30708 of 1982.

ベ ′ しよ°と る −直 ところで、上記の如きN型アノード、P型カソードタイ
プのダイオードにおけるアノードのバンプ電極の形成は
不純物選択数−散が完了した半導体ウェーへの状態で多
数個が一括して行われる。この場合、半導体ウェー八に
おける多数のN−p接合部に一括して逆方向の電圧を印
加してNP接合部をブレークダウンさせ逆方向に電流を
流すことで行われるが、多数のNP接合部の耐圧にバラ
ツキがあってこの耐圧に応じ成長するバンプ電極の高さ
にバラツキが生じることがあった。また半導体ウェー八
に多数形成されたNP’接合部の中に、シ!l −l・
I、た不良なものが在ると、バンプ電極形成時に不良N
P接合部に電流が集中して流れるため、不良NP接合部
の箇所だけにバンプ電極が形成されて他にはバンプ電極
が盛り上がらないが、盛り上がっても縮小で実用に供し
得ない程啓であるといった問題があった。
By the way, the formation of the anode bump electrode in the N-type anode and P-type cathode type diode described above is carried out by placing a large number of bump electrodes at once on a semiconductor wafer after impurity selection and dispersion has been completed. It will be done as follows. In this case, this is done by applying a voltage in the opposite direction to a large number of N-p junctions in the semiconductor wafer all at once to break down the NP junctions and causing current to flow in the opposite direction. There are variations in the breakdown voltage of the bump electrodes, and the height of the bump electrodes grown depending on the breakdown voltage may vary. In addition, there are many NP' junctions formed in the semiconductor wafer. l-l・
I. If there are any defects, defects may occur during bump electrode formation.
Since the current flows concentrated in the P junction, a bump electrode is formed only at the defective NP junction and does not swell anywhere else, but even if it swells, it shrinks and is too small to be of any practical use. There was such a problem.

期し4藍1j友か11 本発明は上記N型アノード、P型カソードタイプのダイ
オードのバンプ電極形成上の問題点に鑑みてなされたも
ので、P型半導体層の表層部に部分的に形成したN型半
導体層上にバンプ電極を形成する方法において、前記P
型、N型半導体層間のPN接合を保護する第1の絶縁膜
上に両生導体層をショートするショート電極を形成する
工程、こ゛のショート電極を前記N型半導体層上のバン
プ電極形成予定部分を除き第2の絶縁膜で被覆する工程
、前記露出したショート電極にメッキ電流を流してバン
プ電極を形成する工程、前記ショート電極を選択的に除
去して前記両生導体層の電気的接続を解く工程とでバン
プ11w5を形成することを特徴とする特許′ある。
The present invention has been made in view of the above-mentioned problems in forming bump electrodes of N-type anode and P-type cathode type diodes. In the method of forming a bump electrode on an N-type semiconductor layer, the P
A step of forming a shorting electrode for shorting the amphibic conductor layer on the first insulating film that protects the PN junction between the semiconductor layer and the N-type semiconductor layer; a step of applying a plating current to the exposed short electrode to form a bump electrode; and a step of selectively removing the short electrode to break the electrical connection between the bidirectional conductor layer. There is a patent 'which is characterized in that the bump 11w5 is formed by

昨月− この技術的手段によるバング電極形成は半導体ウェーハ
の段階で多数個一括して行われるカベ、各バンプ電極は
半導体ウエーノ\に多数形成された上記ショート電極に
流れる電流でもって成長し、ダイオードを形成するNP
接合部の耐圧の大小に関係なく形成される。従って均一
な/Nlンプ電極形成を可能にするー。
Last month - The formation of bump electrodes using this technical means is performed at the stage of a semiconductor wafer in large numbers, and each bump electrode is grown by the current flowing through the short electrodes formed in large numbers on the semiconductor wafer, forming a diode. NPs forming
It is formed regardless of the magnitude of the breakdown voltage of the joint. Therefore, uniform /Nl pump electrode formation is possible.

実施孤 本発明方法の具体的実施例を第1図乃至第3図を参照し
7乍ら以下説明する。
Embodiments Specific embodiments of the method of the present invention will be described from section 7 onwards with reference to FIGS. 1 to 3.

第1図の(イ)〜(へ)は第4図の基本構造のN型アノ
ード、P型カソードクイブダイメ・−ドのバンプ電極形
成工程の本発明による一例を示すもので、第4図と同一
のものには同一参照符号を付して、第1図の(イ)〜(
へ)に基づき説明する。
FIGS. 1A to 1F show an example of the process of forming bump electrodes of the N-type anode and P-type cathode cube die of the basic structure shown in FIG. 4 according to the present invention. The same reference numerals are given to the same items as (a) to (a) in Figure 1.
)).

先ず第1図の(イ)に示すよ・)に′第1の絶縁−膜(
6)のN型半導体層(2)とN型半導体層(3)上の部
分を夫々部分的に除去して窓孔(20)、(21)を形
成する。次に第1図の(ロ)に示すように両窓孔(20
)、(21)及びこの両窓孔(20)、(21)間の絶
縁膜(6)上の一部又は全部を含む範囲でTi−Ag蒸
着薄膜などによるショート電極(22)を被着形成して
、N型半導体rfi(3)とP型半導体層(2)をショ
ートさせる。次に第1図の(ハ)に示すようにショート
1!極(22)のN型半導体層(3)上の所定部分(バ
ンプ電極形成予定部分)を残してショート電ti (2
2) 、拒絶膜(6)上にCVDによる5102.5I
9N4やポリシリコンなどの第2の絶縁膜(23)を被
着形成する。
First, as shown in (a) in Figure 1, the first insulating film (
The portions above the N-type semiconductor layer (2) and the N-type semiconductor layer (3) in step 6) are partially removed to form window holes (20) and (21). Next, as shown in Figure 1 (b), both window holes (20
), (21) and a part or all of the insulating film (6) between the window holes (20), (21) by depositing a short electrode (22) made of a Ti-Ag vapor deposited thin film or the like. Then, the N-type semiconductor rfi (3) and the P-type semiconductor layer (2) are short-circuited. Next, as shown in Figure 1 (c), short 1! A short electrode ti (2
2) 5102.5I by CVD on the rejection membrane (6)
A second insulating film (23) such as 9N4 or polysilicon is deposited.

而して後、第1図の(ニ)に示すようにAgメッキ液内
でP十型半導体基板(1)の裏面にマイナス電圧を印加
し、Agメッキ液内のAg板(24)にプラス電圧を印
加する。すると両半導体層(3)、(2)がショート電
極(22)でショートされているのでメッキ電流IはN
P接合部を流れずショート電極(22)からP″″型半
型体導体層) 、P十型半導体層(1)を流れ、これに
よりショート電極(22)の露出面上にAgプラろイオ
ンが付着してバンプ電極(5°)が成長していく、この
バンプ電極(5゛)はNP接合部の耐圧バラツキに関係
なく均一に成長する。またこのバンプ電極形成は1枚の
半導体ウェーハに多数設けられたNP接合部上で一括し
て行われるが、仮りに1つのNP接合部がショート電極
を起こしていてもショート電極にメッキ電流を流すため
、この不良NP接合部での電流集中の心配が無く、良好
に行える。
After that, as shown in (d) in Figure 1, a negative voltage is applied to the back surface of the P-type semiconductor substrate (1) in the Ag plating solution, and a positive voltage is applied to the Ag plate (24) in the Ag plating solution. Apply voltage. Then, since both semiconductor layers (3) and (2) are shorted by the short electrode (22), the plating current I becomes N.
It does not flow through the P junction but flows from the short electrode (22) to the P'' type semi-conductor layer (1) and through the P ten type semiconductor layer (1), thereby causing Ag plalow ions to form on the exposed surface of the short electrode (22). is deposited and a bump electrode (5°) grows. This bump electrode (5°) grows uniformly regardless of the variation in breakdown voltage of the NP junction. In addition, this bump electrode formation is performed all at once on many NP junctions provided on one semiconductor wafer, but even if one NP junction causes a short electrode, the plating current will not flow through the short electrode. Therefore, there is no fear of current concentration at this defective NP junction, and the process can be performed satisfactorily.

バンプ電極(5°)の形成後、次はショート電極(22
)の不要部分を選択除去する。この除去は、特別のレジ
ストを使用することなく、バンプ電極(5′)をエツチ
ング時のカバーとして利用して、フン酸等によりCVD
による第2の絶縁膜(23)およびショート電極(22
)中のTiを除去したり硝酸等によりショート電極(2
2)中の八gを除去する工程、又は第1図の(ホ)と(
へ)で示す様に、レジストカバーを用いて必要最小限の
ものだけを除去する工程で行われる、即ち、先ず第1図
の(ホ)に示すようにバンプ電極(5′)と絶縁膜(2
3)上の全域にレジストカバー(25)を被着してから
、レジストカバ・−(25)のバンプ電極近傍の部分を
窓開けして窓孔(26)を形成し、この窓孔(26)か
ら絶縁膜(23)をエツチングして部分的に除去する。
After forming the bump electrode (5°), next is the short electrode (22
) to selectively remove unnecessary parts. This removal can be done by using CVD with hydrochloric acid or the like without using a special resist, using the bump electrode (5') as a cover during etching.
The second insulating film (23) and the short electrode (22
) or remove the Ti in the short electrode (2) using nitric acid, etc.
2) Step of removing 8g in the middle, or (e) and (e) in Figure 1
As shown in (e) of Figure 1, this is done in the process of removing only the minimum amount necessary using a resist cover. In other words, first, as shown in (e) of Figure 1, the bump electrode (5') and the insulating film ( 2
3) After applying the resist cover (25) over the entire area, open a window in the vicinity of the bump electrode of the resist cover (25) to form a window hole (26). ), the insulating film (23) is partially removed by etching.

次に絶縁IN (23)の先のエツチングで除去されて
形成された窓孔(27)から第1図の(へ)に示すよう
にショート電極(22)を部分的にエツチングして除去
し、この段階でN型半導体層(3)とP−型半導体層(
2)のショートが解かれて所望のダイオードが得られる
Next, the short electrode (22) is partially etched and removed as shown in FIG. At this stage, the N-type semiconductor layer (3) and the P-type semiconductor layer (
The short circuit 2) is removed and the desired diode is obtained.

次に第5図のパンチスルー型ダイオードの製造に適用し
た本発明の方法を第2図の(イ)〜(ホ)を参照して以
下説明する。
Next, the method of the present invention applied to manufacturing the punch-through diode shown in FIG. 5 will be described below with reference to FIGS. 2A to 2E.

先ず第2図の(イ)、に示すように絶縁膜(16)のN
型半導体層(11)上とPN接合部(15)の表面上に
窓孔(28)、(29)を形成する。尚、PN接合部(
15)の表面部分に予め高不純物濃度のP中型不純物領
域(30)を形成して後のショート電極とのオーミック
性を良好にし、メッキ電流のバイパス領域として利用す
る。次に第2図の(ロ)に示すように窓孔(28)、(
29)と窓孔(28)、(29)間の第1の絶縁膜(1
6)上とにショート電極(31)を被着形成する。次に
第・2図の(ハ)に示すようにショート電極(31)と
絶縁f!ii (16)上との全面にCVDで5i02
などの第2の絶縁膜(32)を被着してからN型半導体
Jti? (11)上のバンプ電極形成予定部分のもの
を選択除去して窓孔(33)を形成する。
First, as shown in FIG. 2(A), the N of the insulating film (16) is
Window holes (28) and (29) are formed on the type semiconductor layer (11) and on the surface of the PN junction (15). In addition, the PN junction (
A medium-sized P impurity region (30) with a high impurity concentration is previously formed on the surface portion of the electrode 15) to improve the ohmic relationship with the subsequent short electrode, and to be used as a bypass region for the plating current. Next, as shown in Figure 2 (b), the window hole (28), (
29) and the first insulating film (1) between the window holes (28) and (29).
6) Form a short electrode (31) on top. Next, as shown in Figure 2 (c), short electrode (31) and insulation f! ii (16) 5i02 on the entire surface with CVD
After depositing the second insulating film (32) such as N-type semiconductor Jti? (11) A window hole (33) is formed by selectively removing the portion on which the bump electrode is to be formed.

而して後、第2図の(ニ)に示すようにメッキ液内でN
生型半導体基板(8)にマイナス、メッキ液中のAg板
(34)にプラスの極性の電圧を印加する。するとショ
ート電極(31)から、(30) −(9) −(8)
の経路でメッキ電流Iが流れて窓孔(33)内にバンプ
電極(13’ )が成長する。後はショート電極(31
)の不要部分を前述の方法で除去する。これは例えば第
2図の(ホ)に示すようにバンプ電極(31)をレジス
トカバーとして利用して絶縁IJ (32)とショート
電極(31)のバンプ電極(13’ )真下のものを除
く全てを順次にエツチングして除去すればよい。この場
合、特にショート電極(31)のエツチング液(フン酸
、硝酸液など)でバンプ電極(13’ )が若干エツチ
ングされるが、ショート電極(31)は厚さが高々1o
ooo人程度であるのに対し、バンプ電極(13’ )
の高さは50μm以上程度もあり、両者間に大差がある
ため問題ない。
After that, as shown in Figure 2 (d), N was added in the plating solution.
A negative voltage is applied to the green semiconductor substrate (8) and a positive voltage is applied to the Ag plate (34) in the plating solution. Then, from the short electrode (31), (30) - (9) - (8)
A plating current I flows through the path, and a bump electrode (13') grows inside the window hole (33). After that, short electrode (31
) are removed using the method described above. For example, as shown in FIG. 2 (e), the bump electrode (31) is used as a resist cover, and all of the insulation IJ (32) and the short electrode (31) except the one directly under the bump electrode (13') They can be removed by sequential etching. In this case, the bump electrode (13') is slightly etched by the etching solution (hydric acid, nitric acid, etc.) for the short electrode (31), but the thickness of the short electrode (31) is at most 100 m.
Bump electrode (13')
The height is about 50 μm or more, and there is a large difference between the two, so there is no problem.

本発明に上記実施例に限らず、特にショート電極の形成
は次のように行ってもよい。例えば、第1図の(ロ)で
示すショート電極形成工程でショート電極(22)を第
3図に示すようにN型半導体層(3)上の中央部分を選
択的に除去しておく。このようにショート電極形成後バ
ンプ電極を形成すると、ショート電極(22)の窓孔(
34)のエツジ部での電界集中化により成長するバンプ
電極(5”°)は中央部分がより高く盛り上がって良好
な山形の形状に仕上がる。また図示しないがバンプ電極
形成のためのショート電極は必ずしも360゛に亘っ゛
ζ形成する必要はなく、例えば後で除去される部分を予
め線状に細く形成して、後のエツチング等による除去を
、容易、迅速ならしめるようにしてもよい。
The present invention is not limited to the above-mentioned embodiments, and in particular, the formation of short electrodes may be performed as follows. For example, in the short electrode forming step shown in (b) of FIG. 1, the central portion of the short electrode (22) on the N-type semiconductor layer (3) is selectively removed as shown in FIG. When the bump electrode is formed after the short electrode is formed in this way, the window hole of the short electrode (22) (
34) By concentrating the electric field at the edges, the bump electrode (5”°) that grows will swell higher in the center and have a good mountain-shaped shape.Also, although not shown, the short electrode for forming the bump electrode is not necessarily It is not necessary to form the ζ over 360 degrees; for example, the portion to be removed later may be formed in advance into a thin line so that later removal by etching or the like can be done easily and quickly.

血ユ少立果 本発明によればN型アノード、P型カソードタイプのダ
イオード等におけるN型アノードのバンプ電極をP型ア
ノ−F、N型カッ−rタイプのダイオードのバンプ電極
と同程度に所望の形で均一に形成することができ、N型
アノード、P型カソードタイプダイオードの多分野での
通用を容易にする。
According to the present invention, the bump electrode of the N-type anode in the N-type anode, P-type cathode type diode, etc. can be made to the same level as the bump electrode of the P-type anode-F, N-type Ka-r type diode. It can be uniformly formed in a desired shape, making it easy for N-type anode and P-type cathode type diodes to be used in many fields.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図はそれぞれ本発明の異なる実施例の製
造方法を説明するための製造工程断面図、第3図は第1
図の一部工程における変更例を示す断面図、第4図及び
第5+v!Jは本発明製造方法の対象となるダイオード
の基本的断面図及び実用的断面図である。 (2) −P型半導体層、(3) −・・N型半導体層
、(5)、(5′)、(5”’ >−バンプ電極、(6
)−・−第1の絶縁膜、(10)・・−P型半導体層、
(11)−N型半導体層、(13)、(13”)・−バ
ンプ電極、(16) −第1の絶縁膜、(22) −シ
ョート電極、(23) −・第2の絶縁膜、(31)−
・−ショート電極、(32) −第2の絶縁膜、I−・
メッキ電流。
1 and 2 are manufacturing process cross-sectional views for explaining manufacturing methods of different embodiments of the present invention, and FIG.
Cross-sectional views showing examples of changes in some of the steps in the figure, Figures 4 and 5 +v! J is a basic cross-sectional view and a practical cross-sectional view of a diode to which the manufacturing method of the present invention is applied. (2) -P-type semiconductor layer, (3) -...N-type semiconductor layer, (5), (5'), (5'''>-bump electrode, (6
)--first insulating film, (10)--P-type semiconductor layer,
(11) - N-type semiconductor layer, (13), (13'') - bump electrode, (16) - first insulating film, (22) - short electrode, (23) - second insulating film, (31)-
・-Short electrode, (32) -Second insulating film, I-・
Plating current.

Claims (1)

【特許請求の範囲】[Claims] (1)P型半導体層の表層部に部分的に形成したN型半
導体層上にバンプ電極を形成する方法において、前記P
型、N型半導体層間のPN接合を保護する第1の絶縁膜
上に両半導体層をショートするショート電極を形成する
工程、このショート電極を前記N型半導体層上のバンプ
電極形成予定部分を除き第2の絶縁膜で被覆する工程、
前記露出したショート電極にメッキ電流を流してバンプ
電極を形成する工程、前記ショート電極を選択的に除去
して前記両半導体層の電気的接続を解く工程とを含むこ
とを特徴とするバンプ電極の形成方法。
(1) In a method of forming a bump electrode on an N-type semiconductor layer partially formed on the surface layer of a P-type semiconductor layer, the P
forming a shorting electrode for shorting both semiconductor layers on a first insulating film that protects the PN junction between the semiconductor layer and the N-type semiconductor layer; a step of covering with a second insulating film;
A bump electrode comprising the steps of: forming a bump electrode by passing a plating current through the exposed short electrode; and selectively removing the short electrode to disconnect the electrical connection between the two semiconductor layers. Formation method.
JP59125742A 1984-06-19 1984-06-19 Forming method of bump electrode Pending JPS614248A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59125742A JPS614248A (en) 1984-06-19 1984-06-19 Forming method of bump electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59125742A JPS614248A (en) 1984-06-19 1984-06-19 Forming method of bump electrode

Publications (1)

Publication Number Publication Date
JPS614248A true JPS614248A (en) 1986-01-10

Family

ID=14917665

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59125742A Pending JPS614248A (en) 1984-06-19 1984-06-19 Forming method of bump electrode

Country Status (1)

Country Link
JP (1) JPS614248A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5242861A (en) * 1991-06-06 1993-09-07 Nec Corporation Method for manufacturing semiconductor device having a multilayer wiring structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5678141A (en) * 1979-11-30 1981-06-26 Hitachi Ltd Method of forming electrode for semiconductor device
JPS5756951A (en) * 1981-08-12 1982-04-05 Hitachi Ltd Manufacture of semiconductor element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5678141A (en) * 1979-11-30 1981-06-26 Hitachi Ltd Method of forming electrode for semiconductor device
JPS5756951A (en) * 1981-08-12 1982-04-05 Hitachi Ltd Manufacture of semiconductor element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5242861A (en) * 1991-06-06 1993-09-07 Nec Corporation Method for manufacturing semiconductor device having a multilayer wiring structure

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