JPS5756951A - Manufacture of semiconductor element - Google Patents

Manufacture of semiconductor element

Info

Publication number
JPS5756951A
JPS5756951A JP12520581A JP12520581A JPS5756951A JP S5756951 A JPS5756951 A JP S5756951A JP 12520581 A JP12520581 A JP 12520581A JP 12520581 A JP12520581 A JP 12520581A JP S5756951 A JPS5756951 A JP S5756951A
Authority
JP
Japan
Prior art keywords
type
bump
forming
layer
type layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12520581A
Other languages
Japanese (ja)
Other versions
JPS5753654B2 (en
Inventor
Heiji Moroshima
Sakae Kikuchi
Hajime Terakado
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12520581A priority Critical patent/JPS5756951A/en
Publication of JPS5756951A publication Critical patent/JPS5756951A/en
Publication of JPS5753654B2 publication Critical patent/JPS5753654B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To enable the formation of a bump due to electrolytic plating in a step of forming the bump electrode of an N-P-N type punch through element by forming a shortcircuit electrode between the N type layer and the P type layer formed with the bumps, thereby facilitating the energization. CONSTITUTION:In a step of manufacturing a punch through constant voltage element, a P type layer 20 and an N<+> type layer 19 are formed on an N<+> type substrate 21, and the layers 19, 20 forming the bump are shortcircuitted with deposited metallic films 7a, 7b. Then, the back surface and the side surface of the substrate 21 are covered with wax 14, an N<+> type layer 21 is connected to a powr source 13, is then dipped in plating liquid 11, plating voltage is applied between the layer and an Ag electrode 12, and a bump is formed between the metallic films 7a and 7b. Then, the substrate 21 is scribed along the region 5, for example, as a DHD type element. Thus, the plating current can be energized through the layer 20, thereby readily forming the uniform bump electrode, and the constant voltage element of low temperature coefficient can be, for example, formed in small size inexpensively.
JP12520581A 1981-08-12 1981-08-12 Manufacture of semiconductor element Granted JPS5756951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12520581A JPS5756951A (en) 1981-08-12 1981-08-12 Manufacture of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12520581A JPS5756951A (en) 1981-08-12 1981-08-12 Manufacture of semiconductor element

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP47099024A Division JPS5751254B2 (en) 1972-10-04 1972-10-04

Publications (2)

Publication Number Publication Date
JPS5756951A true JPS5756951A (en) 1982-04-05
JPS5753654B2 JPS5753654B2 (en) 1982-11-13

Family

ID=14904496

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12520581A Granted JPS5756951A (en) 1981-08-12 1981-08-12 Manufacture of semiconductor element

Country Status (1)

Country Link
JP (1) JPS5756951A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS614248A (en) * 1984-06-19 1986-01-10 Nec Kansai Ltd Forming method of bump electrode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS614248A (en) * 1984-06-19 1986-01-10 Nec Kansai Ltd Forming method of bump electrode

Also Published As

Publication number Publication date
JPS5753654B2 (en) 1982-11-13

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