JPS6232605B2 - - Google Patents
Info
- Publication number
- JPS6232605B2 JPS6232605B2 JP16320779A JP16320779A JPS6232605B2 JP S6232605 B2 JPS6232605 B2 JP S6232605B2 JP 16320779 A JP16320779 A JP 16320779A JP 16320779 A JP16320779 A JP 16320779A JP S6232605 B2 JPS6232605 B2 JP S6232605B2
- Authority
- JP
- Japan
- Prior art keywords
- laminate
- electrode
- hole
- electrodes
- green sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 11
- 238000005498 polishing Methods 0.000 claims description 10
- 238000007772 electroless plating Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 239000000919 ceramic Substances 0.000 claims 4
- 238000010304 firing Methods 0.000 claims 1
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052573 porcelain Inorganic materials 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【発明の詳細な説明】
この発明は、特に貫通型用として最適な積層型
コンデンサの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a multilayer capacitor, particularly suitable for a feedthrough type capacitor.
この種、積層型コンデンサは、中央に貫通穴を
有し、かつ、その一平面上に該平面の外周面のみ
に露出する第1電極が付与されてなる、たとえば
磁器からなる第1誘電体シートと、同じく中央に
貫通穴を有し、かつ、その一平面上に該平面の上
記貫通穴周面のみに露出する第2電極が付与され
てなる第2誘電体シートとを、少なくとも一対、
上記第1、第2両電極が各露出部近傍を除いて重
合し、かつ、貫通穴が連通するように、交互に重
ね合わせて積層体を構成する一方、積層体外周面
と貫通穴内周面に銀などにより互いに電気的に分
離した外部電極面をそれぞれ形成した構成となつ
ている。 This type of multilayer capacitor includes a first dielectric sheet made of, for example, porcelain, which has a through hole in the center and has a first electrode on one plane thereof exposed only on the outer peripheral surface of the plane. and a second dielectric sheet having a through hole in the center and provided with a second electrode on one plane thereof exposed only on the circumferential surface of the through hole on the plane, at least one pair of;
Both the first and second electrodes are overlapped except for the vicinity of each exposed portion, and are stacked alternately to form a laminate so that the through holes communicate with each other, while the outer peripheral surface of the laminate and the inner peripheral surface of the through hole The structure is such that external electrode surfaces electrically isolated from each other are formed using silver or the like.
ところが、上記した積層型コンデンサの外部電
極の形成方法は、上記積層体の外周面および貫通
穴内周面に、導電性の金属ペイントを筆やブラシ
で塗布し、その後焼付けるという手段を採つてい
るため、1個づつ手作業で行なわなければなら
ず、生産性が非常に悪く、品質にもバラツキを生
じる欠点があつた。 However, the method for forming the external electrode of the multilayer capacitor described above employs a method of applying conductive metal paint to the outer circumferential surface of the multilayer body and the inner circumferential surface of the through hole with a brush or a brush, and then baking it. Therefore, each piece had to be done manually, which resulted in very low productivity and a drawback of uneven quality.
また、この方法では、外部電極を筆やブラシで
塗布するために、その外部電極厚を一様にでき
ず、その外径や内径の寸法が均一とできないとい
う欠点があり、特にこれを貫通型として用いる場
合には、ケースへの装填や貫通軸の挿通が円滑に
行なえないという大きな問題があつた。さらに小
型のものを製造する場合には、筆やブラシで塗布
する際に、いわゆるはみ出し部が生じ易く、対向
外部電極間の短絡事故を招来していた。しかも、
この外部電極には、作業性等の点から銀が用いら
れているが、この銀はマイグレイシヨン等が発生
し易いという懸念もあり、寿命特性にも優れたも
のではなかつた。 In addition, this method has the disadvantage that the external electrode is applied with a brush or brush, so the thickness of the external electrode cannot be made uniform, and the dimensions of the outer diameter and inner diameter cannot be made uniform. When used as such, there was a major problem in that loading the case and inserting the through shaft into the case could not be carried out smoothly. Furthermore, when manufacturing smaller products, when applying with a brush or a brush, so-called protruding parts are likely to occur, resulting in a short circuit between opposing external electrodes. Moreover,
Silver is used for this external electrode from the viewpoint of workability, but there is also a concern that migration is likely to occur with this silver, and it does not have excellent life characteristics.
この発明は上記欠点に鑑みてなされたものであ
つて、それぞれ貫通穴を有し、かつ、露出部を互
いに異ならせた第1、第2誘電体シートを交互
に、上記貫通穴が連通するように積層して構成し
た積層体全体に、無電解メツキにより外部電極を
施した後、平面研摩処理して互いに電気的に分離
した外部接続用電極、つまり、積層体外周電極お
よび貫通穴内周電極を形成するようにして、多量
生産を行なうことができ、しかも、品質のバラツ
キの少ない精度の高い、特に貫通型用として有用
な積層型コンデンサの製造方法を提供しようとす
るものである。 This invention was made in view of the above-mentioned drawbacks, and the first and second dielectric sheets each having a through-hole and having different exposed portions are alternately arranged so that the through-holes communicate with each other. After applying external electrodes to the entire laminate by electroless plating, surface polishing is performed to electrically separate external connection electrodes from each other, that is, electrodes on the outer periphery of the laminate and electrodes on the inner periphery of the through holes. It is an object of the present invention to provide a method for manufacturing a multilayer capacitor, which can be mass-produced by forming the capacitor, has high precision with little variation in quality, and is particularly useful for through-type capacitors.
以下、この発明を図面に示す一実施例で詳細に
説明する。 Hereinafter, this invention will be explained in detail with reference to an embodiment shown in the drawings.
この発明の製造方法にかかる積層型コンデンサ
は、第1図に示すように、中心部にそれぞれ貫通
穴1a,2aを有する少なくとも一対のドーナツ
状の第1、第2誘電体シート1,2を用意する。 As shown in FIG. 1, the multilayer capacitor according to the manufacturing method of the present invention includes at least a pair of donut-shaped first and second dielectric sheets 1 and 2 each having a through hole 1a and 2a in the center. do.
この一対の第1、第2誘電体シート1,2のう
ち、一方の第1誘電体シート1の上面1bには、
第1誘電体シート1の貫通穴1aと同一内径で、
かつ、第1誘電体シート1の直径よりも小さな外
径のパラジウム、プラチナあるいはこれらの合金
などからなる第1電極3を塗布あるいは印刷によ
り形成する。また、他方の上記第2誘電体シート
2の上面2bには、第1誘電体シート1と同様に
して、第2誘電体シート2の直径と同一の外径を
有し、かつ、貫通穴2aよりも大きい内径を有す
る上記同一材質の第2電極4を上記と同一の手法
で形成する。したがつて、上記第1電極3は、上
記第1誘電体シート1の貫通穴1aの外周面側に
露出することになり、上記第2電極4は上記第2
誘電体シート2の内周面側に露出することにな
る。 Among the pair of first and second dielectric sheets 1 and 2, on the upper surface 1b of one of the first dielectric sheets 1,
With the same inner diameter as the through hole 1a of the first dielectric sheet 1,
Further, a first electrode 3 made of palladium, platinum, an alloy thereof, or the like and having an outer diameter smaller than the diameter of the first dielectric sheet 1 is formed by coating or printing. Further, the upper surface 2b of the other second dielectric sheet 2 has a through hole 2a having the same outer diameter as the diameter of the second dielectric sheet 2, similarly to the first dielectric sheet 1. A second electrode 4 made of the same material as described above and having an inner diameter larger than that is formed by the same method as described above. Therefore, the first electrode 3 is exposed on the outer peripheral surface side of the through hole 1a of the first dielectric sheet 1, and the second electrode 4 is exposed on the outer peripheral surface side of the through hole 1a of the first dielectric sheet 1.
It will be exposed on the inner peripheral surface side of the dielectric sheet 2.
このようにして構成された第1、第2誘電体シ
ート1,2を、第2図に示すように、交互に適宜
枚数積層するとともにその上部にダミーシートと
して電極の付与されていない誘電体シート5を1
枚以上載置して、積層体Xを構成する。この場
合、通常は上記積層体Xの下部にも1枚以上のダ
ミーシートが設けられる。 As shown in FIG. 2, the first and second dielectric sheets 1 and 2 constructed in this manner are alternately laminated in an appropriate number, and a dielectric sheet without electrodes is placed on top as a dummy sheet. 5 to 1
A laminate X is formed by placing at least one of them. In this case, one or more dummy sheets are usually provided under the laminate X as well.
この積層体X、すなわち、それぞれ第1、第2
電極3,4が付与されている複数の第1、第2誘
電体シート1,2は、プレス等によつて圧縮して
焼成し、各第1、第2電極3,4を同時に焼き付
ける。 This laminate X, that is, the first and second
The plurality of first and second dielectric sheets 1 and 2 provided with electrodes 3 and 4 are compressed and fired using a press or the like, and the first and second electrodes 3 and 4 are simultaneously fired.
つづいて、第3図に示すように、積層体Xの上
下面における角部Xa,Xaおよび貫通部Xbの上下
における角部Xc,Xcの面取りをバレル研摩等に
より行なつて、円孤面に形成する。 Next, as shown in FIG. 3, the corners Xa, Xa on the upper and lower surfaces of the laminate X and the corners Xc, Xc on the upper and lower sides of the through-hole Xb are chamfered by barrel polishing or the like to form circular arc surfaces. Form.
上記積層体Xの各角部Xa,XaおよびXc,Xcの
面取り作業終了後、第4図に示すように、積層体
X全体を、図示しない無電解メツキ槽に浸漬し
て、銅、ニツケルなどの無電解メツキ膜を付与
し、たとえば、約4μm程の外部電極Sを形成す
る。この場合、上記無電解メツキ膜を形成した
後、適宜熱処理を施してもよい。 After chamfering the corners Xa, Xa and Xc, Xc of the laminate X, as shown in FIG. 4, the entire laminate An electroless plating film of, for example, approximately 4 μm in thickness is formed. In this case, after forming the electroless plating film, heat treatment may be performed as appropriate.
積層体Xの全表面に外部電極Sを形成した後、
第5図に示すように、平面研摩によつて、積層体
Xの上下面、すなわち、積層体Xの上下に位置す
る誘電体シート2,5の上下面における外部電極
Sを研摩する。これにより、第5図に示すよう
に、互いに電気的に分離された積層体Xの外周電
極SAと、貫通穴XBの内周電極SBとに分割す
る。そして、この外周電極SAは上記各第2電極
4に電気的に接続され、内周電極SBは上記第1
電極3に電気的に接続されることになる。 After forming the external electrode S on the entire surface of the laminate X,
As shown in FIG. 5, the external electrodes S on the upper and lower surfaces of the laminate X, that is, the upper and lower surfaces of the dielectric sheets 2 and 5 located above and below the laminate X, are polished by surface polishing. As a result, as shown in FIG. 5, the stacked body X is divided into an outer electrode S A of the stacked body X and an inner electrode S B of the through hole X B , which are electrically isolated from each other. The outer electrode S A is electrically connected to each of the second electrodes 4, and the inner electrode S B is connected to the first electrode 4.
It will be electrically connected to the electrode 3.
上記のようにして、極めて簡単な作業を順次行
なうだけで、バラツキのない同一品質の積層型コ
ンデンサを製造することができる。なお、この発
明において使用される誘電体シートの形状は、図
示のような円形のものに限ることはない。 As described above, multilayer capacitors of uniform quality can be manufactured by performing extremely simple operations one after another. Note that the shape of the dielectric sheet used in the present invention is not limited to the circular shape shown in the drawings.
以上のように、この発明にかかる製造方法によ
れば、電極の付与された少なくとも一対の誘電体
シートをそれぞれ交互に積み重ねて焼成し、積層
体を構成した後、面取り処理を行ない、その後積
層体全表面に、無電解メツキにより外部電極を形
成し、この後に積層体上下面を研摩して、互いに
電気的に分離した積層体外周電極と貫通穴内周電
極とに分割するだけの簡単な工程からなるので、
量産が可能となり、しかも、同一品質の積層型コ
ンデンサを製造することができる。 As described above, according to the manufacturing method of the present invention, at least one pair of dielectric sheets provided with electrodes are alternately stacked and fired to form a laminate, and then a chamfering process is performed, and then the laminate is From the simple process of forming external electrodes on the entire surface by electroless plating, and then polishing the top and bottom surfaces of the laminate to divide it into an electrode on the outer periphery of the laminate and an electrode on the inner periphery of the through hole, which are electrically isolated from each other. So,
Mass production becomes possible, and multilayer capacitors of the same quality can be manufactured.
すなわち、面取り処理には、バレル研摩法、上
下面の研摩には平面研摩法、また外部電極の付与
には無電解メツキ法という、いずれも量産性のす
ぐれた手法を採用することができる。 That is, the barrel polishing method can be used for chamfering, the flat polishing method can be used for polishing the upper and lower surfaces, and the electroless plating method can be used for applying external electrodes, all of which are excellent in mass production.
また、外部電極の形成は、無電解メツキにより
行なうので、メツキ層は薄く、かつ、均一な厚み
にでき、寸法精度にすぐれそれだけ研摩作業を簡
単化でき、さらに、銀を使用しないのでマイグレ
イシヨンが生じないことも相俟つてダミーシート
としての誘電体シートを必要最小厚みとすること
ができ、材料の無駄をなくすことができるととも
に、コンデンサ本体の小型化を促進する。 In addition, since the external electrodes are formed by electroless plating, the plating layer can be thin and have a uniform thickness, and the dimensional accuracy is excellent, which simplifies the polishing work.Furthermore, since no silver is used, migration is easy. Coupled with this fact, the dielectric sheet serving as a dummy sheet can be made to have the minimum required thickness, thereby eliminating waste of materials and promoting downsizing of the capacitor body.
しかも、外部電極を形成した積層体の上下面の
角部および貫通穴の上下角部には、面取りを施し
ているので、平面研摩時における内外周電極の剥
離を確実に防止でき、品質の向上を図ることがで
きる。 Furthermore, the corners of the upper and lower surfaces of the laminate on which the external electrodes are formed and the upper and lower corners of the through holes are chamfered, which reliably prevents the inner and outer peripheral electrodes from peeling off during surface polishing, improving quality. can be achieved.
第1図はこの発明の製造方法にかかる積層コン
デンサに用いる誘電体シートの形状例を示す概略
斜視図、第2図は第1図の絶縁体シートを積層し
た状態を示す概略斜視図、第3図は第2図に示し
た積層体の面取処理後の状態を示す概略斜視図、
第4図は、無電解メツキを施した状態を示す概略
斜視図、第5図は無電解メツキ処理後に積層体の
研摩処理を行なつた状態を示す概略斜視図であ
る。
1,2……第1、第2誘電体シート、1a,2
a……貫通穴、3,4……第1、第2電極、5…
…ダミーシート、X……積層体、Xa……積層体
上下面角部、Xb……積層体貫通穴、Xc……貫通
穴上下角部、S……外部電極、SA……外周電
極、SB……内周電極。
1 is a schematic perspective view showing an example of the shape of a dielectric sheet used in a multilayer capacitor according to the manufacturing method of the present invention, FIG. 2 is a schematic perspective view showing a state in which the insulator sheets of FIG. 1 are laminated, and FIG. The figure is a schematic perspective view showing the state of the laminate shown in FIG. 2 after chamfering treatment,
FIG. 4 is a schematic perspective view showing a state in which electroless plating has been applied, and FIG. 5 is a schematic perspective view showing a state in which a laminate has been polished after electroless plating. 1, 2...first and second dielectric sheets, 1a, 2
a...Through hole, 3, 4...First, second electrode, 5...
...Dummy sheet , S B ...Inner circumferential electrode.
Claims (1)
ーンシートの一平面上に該シートの外周面にのみ
露出する第1電極を付与する一方、同じく中央部
に貫通穴を有する第2誘電体磁器グリーンシート
の一平面上に上記貫通穴周面にのみ露出する第2
電極を付与し、かつ上記第1誘電体磁器グリーン
シートと第2誘電体磁器グリーンシートとを少な
くとも一対、電極の付与されていないグリーンシ
ートからなるダミーシートとともに積み重ねて積
層体を構成し、この積層体を焼成し、この積層体
の上下面角部および上記貫通穴の上下角部の面取
り処理を行なつた後、積層体全面に無電解メツキ
を施して外部電極を形成し、その後この積層体の
上下面を研摩処理して、上記外部電極を互いに電
気的に分離した貫通穴内周電極と、積層体外周電
極とに分割形成して構成するようにしたことを特
徴とする積層型コンデンサの製造方法。1. A first dielectric ceramic green sheet having a through hole in the center is provided with a first electrode exposed only on the outer peripheral surface of the sheet on one plane, while a second dielectric ceramic green sheet also having a through hole in the center is provided. A second plate exposed only on the circumferential surface of the through hole on one plane of the green sheet.
At least one pair of the first dielectric ceramic green sheet and the second dielectric ceramic green sheet provided with electrodes are stacked together with a dummy sheet consisting of a green sheet to which no electrodes are provided to form a laminate, and this laminate is formed. After firing the body and chamfering the top and bottom corners of this laminate and the top and bottom corners of the through holes, electroless plating is applied to the entire surface of the laminate to form external electrodes, and then this laminate is Manufacturing a multilayer capacitor characterized in that the external electrode is formed by polishing the upper and lower surfaces of the capacitor, and the external electrode is divided into a through-hole inner electrode and a multilayer outer electrode, which are electrically separated from each other. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16320779A JPS5685816A (en) | 1979-12-15 | 1979-12-15 | Method of manufacturing laminated condenser |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16320779A JPS5685816A (en) | 1979-12-15 | 1979-12-15 | Method of manufacturing laminated condenser |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5685816A JPS5685816A (en) | 1981-07-13 |
JPS6232605B2 true JPS6232605B2 (en) | 1987-07-15 |
Family
ID=15769316
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16320779A Granted JPS5685816A (en) | 1979-12-15 | 1979-12-15 | Method of manufacturing laminated condenser |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5685816A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61142727A (en) * | 1984-12-17 | 1986-06-30 | 松下電器産業株式会社 | Metalized film capacitor |
-
1979
- 1979-12-15 JP JP16320779A patent/JPS5685816A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5685816A (en) | 1981-07-13 |
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