JPS6231495B2 - - Google Patents
Info
- Publication number
- JPS6231495B2 JPS6231495B2 JP54036863A JP3686379A JPS6231495B2 JP S6231495 B2 JPS6231495 B2 JP S6231495B2 JP 54036863 A JP54036863 A JP 54036863A JP 3686379 A JP3686379 A JP 3686379A JP S6231495 B2 JPS6231495 B2 JP S6231495B2
- Authority
- JP
- Japan
- Prior art keywords
- package body
- cap
- semiconductor chip
- package
- connection terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 12
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 239000012945 sealing adhesive Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、多数の外部接続端子を有するICパ
ツケージすなわち、半導体装置に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an IC package, ie, a semiconductor device, having a large number of external connection terminals.
LSIパツケージ等のICパツケージは必然的に外
部接続端子が多く、その外部接続端子としてピン
を用いる従来の一般的構造のLSIパツケージで
は、ピンはパツケージ本体の周辺部にのみ配置さ
れるのでピンの配置密度に限度があり、又特別の
放熱手段を持つていないので、容量的な面からも
制限を受ける。パツケージの側面からリードを導
出する方式もあるが、側面は面積が少ないので必
然的にリードの導出密度が高くなり、ハンドリン
グの面で不利である。 IC packages such as LSI packages inevitably have many external connection terminals, and in conventional LSI package structures that use pins as external connection terminals, the pins are placed only on the periphery of the package body, so the pin arrangement There is a limit in density, and since it does not have a special heat dissipation means, it is also limited in terms of capacity. There is also a method of leading out the leads from the side of the package, but since the side surface has a small area, the lead out density is inevitably high, which is disadvantageous in terms of handling.
本発明は、このような欠点を除去し、接続端子
手段の密度を高くすることなどができ、しかも放
熱性の良好な、半導体装置を提供することを目的
とするものである。 SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which can eliminate such drawbacks, can increase the density of connection terminal means, and has good heat dissipation.
この目的を達成するために、本発明の一実施例
では、半導体装置において半導体チツプをパツケ
ージ本体の一主面上に固着せしめ、前記半導体チ
ツプ上に設け前記パツケージ本体と固着するキヤ
ツプとからなり、上記パツケージ本体のキヤツプ
が配置される面に上記半導体チツプ外部接続端子
として機能する多数のハンダドツトを形成し、所
望によりパツケージ本体のキヤツプ配置側とは反
対の面に、放熱体を取付けたものである。 In order to achieve this object, one embodiment of the present invention includes a semiconductor device in which a semiconductor chip is fixed on one main surface of a package body, and a cap provided on the semiconductor chip and fixed to the package body; A large number of solder dots functioning as external connection terminals for the semiconductor chip are formed on the surface of the package body where the cap is placed, and a heat sink is attached, if desired, to the side of the package body opposite to the side where the cap is placed. .
第１図及び第２図は本発明の一実施例を示すも
のであり、以下これに基づいて更に詳細に説明す
る。 FIG. 1 and FIG. 2 show one embodiment of the present invention, which will be described in more detail below.
１は積層セラミツクから成るパツケージ本体で
あつて、その中央部に形成された凹所２にICチ
ツプ３が取付けられている。ICチツプ３を収納
した凹所は封止接合剤層４を介してキヤツプ５に
より封止される。パツケージ本体１の、キヤツプ
５の周辺の端面には複数のハンダドツト６が形成
されている。これらのハンダドツト６は、パツケ
ージ本体中を貫挿するメタライズ層７を介して凹
所２内に電気的に導かれ、ボンデイングワイヤ８
を介してICチツプ３の対応する端子箇所に接続
される。パツケージ本体１の、キヤツプ５とは反
対側の面には、多数の凹凸を付けて放熱表面積を
増加させた放熱体９が装着されている。 1 is a package body made of laminated ceramic, and an IC chip 3 is mounted in a recess 2 formed in the center thereof. The recess housing the IC chip 3 is sealed with a cap 5 via a sealing adhesive layer 4. A plurality of solder dots 6 are formed on the end surface of the package body 1 around the cap 5. These solder dots 6 are electrically guided into the recess 2 via a metallized layer 7 that penetrates through the package body, and are connected to bonding wires 8.
The terminals are connected to the corresponding terminals of the IC chip 3 through the terminals. A heat sink 9 is attached to the surface of the package body 1 opposite to the cap 5, and has a large number of projections and depressions to increase the heat radiation surface area.
このように外部接続端子をハンダドツト６とし
て形成することにより外部接続端子およびこれら
の端子を設置面に保持するための剛性を持たせる
構造が接続端子の周囲に不要となるため、高密度
の端子配置が容易となり、より高密度かつ小型の
LSIを構成することが可能となり、しかもLSI単
体のハンドリングが容易になる。又、放熱体９を
設けることにより放熱効果は著しく向上する。 By forming the external connection terminals as solder dots 6 in this way, there is no need for external connection terminals and a rigid structure around the connection terminals to hold these terminals on the installation surface, allowing for high-density terminal arrangement. This makes it easier to create denser and smaller
It becomes possible to configure an LSI, and it also becomes easier to handle the LSI alone. Furthermore, by providing the heat sink 9, the heat radiation effect is significantly improved.
なお、キヤツプ５はパツケージ本体１の端面か
ら突出しないように埋込式にしてもよいが、図示
のごとくパツケージ本体１の端面から突出させる
ことにより、これを位置決め部材として利用でき
るので便利である。 Although the cap 5 may be of an embedded type so that it does not protrude from the end surface of the package body 1, it is convenient to make it protrude from the end surface of the package body 1 as shown, since it can be used as a positioning member.
更に、第３図に示すように、一面側がLSIパツ
ケージの端子側の面と対応する形状に形成されて
係合可能であり、かつハンダドツト６に対向する
位置にそれぞれ対応するハンダドツト１１を形成
し、他面側にハンダドツト１１に電気的につなが
る内部結線を施した接続ピン１２を配置して成る
接続ベース１０を用いれば、外部接続端子として
接続ピン１２が平面上にぎつしり並んだ抜き差し
自在のLSIを構成することができる。 Furthermore, as shown in FIG. 3, one surface side is formed in a shape corresponding to the terminal side surface of the LSI package so that it can be engaged therewith, and solder dots 11 are formed corresponding to the positions facing the solder dots 6, respectively. If a connection base 10 is used, which has connection pins 12 electrically connected to solder dots 11 on the other side, the connection pins 12 can be freely inserted and removed as external connection terminals, and the connection pins 12 are tightly arranged on a plane. can be configured.
第１図は本発明によるLSIパツケージの一実施
例を示す断面図、第２図は第１図の要部の拡大
図、第３図は第１図のLSIパツケージに組合わせ
て用いる接続ベースの側面図である。
１…パツケージ本体、２…凹所、３…ICチツ
プ、５…キヤツプ、６…ハンダドツト、７…メタ
ライズ層、８…ボンデイングワイヤ、９…放熱
体。
Fig. 1 is a sectional view showing an embodiment of the LSI package according to the present invention, Fig. 2 is an enlarged view of the main parts of Fig. 1, and Fig. 3 is a connection base used in combination with the LSI package of Fig. 1. FIG. DESCRIPTION OF SYMBOLS 1... Package body, 2... Recess, 3... IC chip, 5... Cap, 6... Solder dot, 7... Metallized layer, 8... Bonding wire, 9... Heat sink.
Claims (1)
固着せしめ、前記半導体チツプ上に設け前記パツ
ケージ本体と固着するキヤツプとからなり、上記
パツケージ本体のキヤツプが配置される面に上記
半導体チツプの外部接続端子として機能する多数
のハンダドツトを形成したことを特徴とする半導
体装置。 ２ 上記パツケージ本体の半導体チツプが固着さ
れている主平面と対向する他の主平面に放熱体が
装着されていることを特徴とする特許請求の範囲
第１項記載の半導体装置。[Scope of Claims] 1. A semiconductor chip is fixed on one main surface of a package body, a cap is provided on the semiconductor chip and fixed to the package body, and the above-mentioned cap is attached to the surface of the package body on which the cap is disposed. A semiconductor device characterized by forming a large number of solder dots that function as external connection terminals of a semiconductor chip. 2. The semiconductor device according to claim 1, wherein a heat sink is mounted on another main plane of the package body opposite to the main plane to which the semiconductor chip is fixed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3686379A JPS55130155A (en) | 1979-03-30 | 1979-03-30 | Ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3686379A JPS55130155A (en) | 1979-03-30 | 1979-03-30 | Ic package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55130155A JPS55130155A (en) | 1980-10-08 |
| JPS6231495B2 true JPS6231495B2 (en) | 1987-07-08 |
Family
ID=12481613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3686379A Granted JPS55130155A (en) | 1979-03-30 | 1979-03-30 | Ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55130155A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5521109A (en) * | 1978-08-02 | 1980-02-15 | Oki Electric Ind Co Ltd | Package for accommodating semiconductor parts |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52137769U (en) * | 1976-04-13 | 1977-10-19 |
-
1979
- 1979-03-30 JP JP3686379A patent/JPS55130155A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5521109A (en) * | 1978-08-02 | 1980-02-15 | Oki Electric Ind Co Ltd | Package for accommodating semiconductor parts |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55130155A (en) | 1980-10-08 |
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