JPS6230491A - Still picture display device - Google Patents

Abstract

PURPOSE:To display a natural picture of high picture quality with limited memory capacity by providing a memory that stores information that discriminates the difference between the state of storage of natural picture information and character graphic information. CONSTITUTION:Character graphic information is supplied from a keyboard 6 to a RAM 4, and picture information is supplied from a picture input terminal to a CPU by telephone, etc. Picture information stored in the CPU 1 is confirmed by information stored in the RAM 4 that it is designated picture information, and written on a frame memory 10 when a switching circuit 9 is switched to a bus 17. At this time, if it is judged as encoded character graphic information, it is converted to character pattern referring to a ROM 5, and written on the memory 10. When it is judged as high-efficiently encoded natural picture information, it is written on the memory 10 as it is. Color designation information is converted to color information by a color conversion circuit 11, and natural picture information is decoded by a decoding circuit 12 and supplied respectively to a switching circuit 13, and either of picture signals is selected and converted to analog information and outputted to a display device.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides a method for accessing a center via, for example, a telephone network;
The invention relates to a still image display device that can receive information such as text and graphics from the center and display it as a still image at home, etc. More specifically, it can display not only text and graphics but also natural images mixed with it. Still image display bag ff1Kr that can also display images! 4.

[Background of the invention]

Devices that transmit and display still images using radio waves and telephone networks do not only transmit and display simple character and graphic information such as that in teletext and captain systems, but also transmit and display static images that can be seen on general television broadcasts. Research is being conducted on transmitting and displaying natural image information as well.

For example, natural image display as described in the paper ``Digital Still Image Display Device'' described on pages 159 to 171 of Research and Practical Application Report End 33 Spring No. 8 of the Telecommunications Research Institute of Nippon Telegraph and Telephone Public Corporation. A good example of this is the function, and an example of the use of such a function is to use it as an insert photo in a newspaper, etc. In other words, if the page of the newspaper is a still image display of characters and figures, photographs are inserted here and there on the page of the newspaper. However, similar to this, a use is being considered in which natural am is inserted here and there on the #plan display M side of text and graphics to display a still image.

However, while simple character and graphic information can be expressed with a few bits per pixel, natural image information requires a precision of 5 bits or more even for a single color to avoid false contours, and has the problem of requiring a large amount of memory capacity. Ta.

To address these problems, the aforementioned paper ``Digital Still Image In-Home Device'' decomposes one pixel of natural image information into three primary colors, red, green, and blue, and allocates 5 bits to each, which is also used as memory for displaying text and graphic information. We are proposing a method for using it.

However, in this case, even though the frame memory has a large capacity of about 100 kilobytes, the resolution is rough at 248 dots horizontally and 204 dots vertically, and the image quality is still not sufficient for a natural image. There wasn't.

Furthermore, since a frame memory with a large capacity is required to display natural image information, conventional still image display devices with small memory capacities cannot have a natural m-image display function.

[Purpose of the invention]

An object of the present invention is to eliminate the drawbacks of the above-mentioned prior art and to provide a still image display device that enables higher quality natural image display with limited memory capacity, in other words, a small memory that enables natural image display. An object of the present invention is to provide a capacitive still image display device.

[Summary of the invention]

In order to achieve the above object, the present invention provides a still image display device that encodes natural image information with high efficiency coding such as differential PCM, transmits it, receives it and displays it, and uses part or all of its frame memory. The natural image information is stored in the encoded state.

Furthermore, other character and graphic information is decomposed into image patterns and stored in the frame memory, and a memory is also provided to store information that identifies the difference in these storage states. By switching the reproduction means, it is possible to reproduce natural image information and text/graphic information on the same screen.

In other words, display 1 when viewed chronologically like natural image information.
Taking advantage of this fact, pixel information that has a strong correlation with the information before the pixel is stored in the frame memory as a high-efficiency code, while information that has a weak correlation and a small number of colors, such as character and graphic information, is decomposed into image patterns. The image is stored in a 7-frame memory for image reproduction, thereby reducing the memory capacity used for the frame memory of the entire apparatus.

Here, some explanation will be added regarding the above-mentioned high efficiency code.

If natural image information is 8 bits per code, it is assumed that it is represented by an 8-bit code (general code). Generally, natural images often change gradually when viewed in time series, and information about the current pixel often has a strong correlation with information about the previous pixel. Therefore, regarding natural image information, when comparing the 8 bits that make up one code with the 8 bits of the previous code in chronological order, if the correlation is strong, the 8 bits that make up one code are
Only the lower 4 bits of the bits change, and the upper 4 bits change.
In many cases, bits have not changed.

In such a case, instead of transmitting a general code (8 bits), only the lower 4 bits are used as a high-efficiency code and are transmitted together with information representing this (usually 1 bit).

In addition, in a part where the information content changes rapidly, such as the @circle part of the i source, if the 8 bits that make up one code of natural image information are compared with the 8 bits of the previous code in time series,
Changes may extend to the upper 4 bits. At this time, the upper 4 bits are transmitted as a high-efficiency code together with information (usually 1 bit) representing this.

By doing this, the memory capacity can be reduced when transmitting and storing high-efficiency codes, compared to when transmitting and storing general codes.

However, when displaying a natural image on a display, it is necessary to convert the high-efficiency code (4 bits) back to a general code (8 bits) before inputting it to the display (CRT). When restoring, assuming that the high-efficiency code to be processed now has the upper 4 bits, "0000" is unconditionally added as the lower 4 bits to return it to an 8-bit code, and the high-efficiency code to be processed is returned to the 8-bit code. If it is the lower 4 bits, the upper 4 bits to be added are:
Before that, the upper 4 bits, which were also sent as a high-efficiency code, are stored and added.

The operating principle of the present invention has now been understood more specifically.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using Examples.

FIG. 1 is a block diagram showing a still image display device as an embodiment of the present invention.

In the figure, 1 is an integrated central processing circuit (hereinafter referred to as CPU), 2 is a clock generation circuit that generates various clocks and timing signals, and 3 is a memory (hereinafter referred to as a program 4 is a rewritable memory (hereinafter referred to as data RAM), and 5 is a memory to be referred to when converting character codes into character patterns to be displayed (hereinafter referred to as character pattern R).
OM), 6 is a keyboard, 7 is a keyboard ink 7 ace circuit, 8 is an image information interface circuit, 9 is a switching circuit for switching address information from the CPU 1 and read address information from the clock generation circuit 2, 10
11 is a frame memory that stores image information to be displayed;
12 is a color conversion circuit that converts color designation information into color information among the image information stored in the frame memory; 12 is encoded image information stored in the frame memory, that is, a memory-saving information format in the form of a high-efficiency code; 13 is a color conversion circuit 11 and a decoding circuit 12.
14 is a D/A conversion circuit that converts a digital image signal into an analog signal; 15 is a circuit that inputs image information to the still image display device from a telephone network (not shown), etc. An image information input terminal 16 is a display information output terminal for outputting display information to a display device such as a cathode ray tube, and 17 is a path for supplying a CPUI address signal, data signal, etc.

The basic operation of this device is as follows.

Information such as the screen number specified from the keyboard 6 is stored in the data RAM 4 via the keyboard interface circuit 7. On the other hand, image information input from the image information input terminal 15 via a telephone network or the like is taken into the CPU 1 via the image information input interface circuit 8, and is inputted into the image information specified by the information stored in the data box AM4. When the existence of the data is confirmed and the switching circuit 9 is switched to the bus 17 side, it is written into the frame memory 10.

At this time, if it is determined to be encoded character graphic information, the character pattern ROM 5 is referred to, the character pattern is converted to a character pattern, and the converted character pattern is written into the frame memory 10 as color designation information.

Furthermore, if it is determined that the natural image information has been highly efficiently encoded, it is written directly into the frame memory 10 in the form of a high-efficiency code. These processing procedures are stored in the program ROM 3.

Furthermore, the image information stored in the frame memory 10 is
In the case of color designation information such as the above-mentioned character pattern, it is converted into color information by the color conversion circuit 11 and sent to the switching circuit 13, and in the case of highly efficient encoded natural image information, it is sent to the general public by the decoding circuit 12. It is decoded into the original image information in encoded format and is supplied to the fJJ switching circuit 13, and then the switching circuit 1
In step 3, one of the image signals is selected and supplied to the D/A conversion circuit 14.

The D/A conversion circuit converts the image as input digital information into analog information and outputs it to a display device such as a cathode ray tube (not shown), to the display information output terminal 16. This analog information to be displayed is output.

The above is an explanation of the basic operation of the still image display device shown in FIG. is stored as an image pattern, and if the image information stored in the frame memory 10 has a strong correlation with information one pixel before display, such as natural image information, it is stored as a high-efficiency code as described above. Therefore, the memory capacity used in the frame memory 10 of the entire apparatus can be reduced compared to the conventional example in which all natural image patterns are stored.

Next, the decoding circuit 12 shown in FIG. 1, which is the main circuit in the present invention, will be explained in more detail.

FIG. 2 is a detailed circuit diagram of the main part including the decoding circuit 12 in FIG. 1, and FIG. 3 is an explanatory diagram for explaining the circuit operation of FIG. 2.

In FIG. 2, the same circuit blocks as in No. 11 are denoted by the same symbols. In the figure, 18 to 23 in the frame memory 10 are ftAMs for storing image information, etc., and 24 to 29 are serial to parallel conversion circuits (hereinafter referred to as SPs) for converting parallel signals read from each RAM into serial signals. (abbreviated as conversion circuit).

In addition, 30 in the color conversion circuit 11 is CPUIC)
A multiplexer 31 switches between a bus signal and an image signal read out from the frame memory 10, and a color conversion RAM 31 stores color conversion information. Further, 32 to 34 in the switching circuit 13 are multiplexers. In the decoding circuit 12, 35 is a 4-pitch F latch for storing the upper bits of natural image information (that is, the upper 4 bits in a high-efficiency code format), 36 is a multiplexer, 37 is an AND circuit, and 38 is a 4 bit latch, 39
is a comparator for identifying the direction of increase/decrease in the upper bits of natural image information.

It is assumed that image information for displaying a screen including a natural image area 50 as shown in FIG. 3(a) is stored in the RAM 18 to RAM 23 by the CPU.

That is, if image information along the horizontal scanning direction indicated by line AA in FIG. 3(a) is expressed as shown in FIG. 3(b), the signals outputted via the SP conversion circuits 24 to 29 25 to Zo become information as shown in FIG. 3(C). That is, the output signal Z5 read out from the RAM 18 and the SP conversion circuit 24 represents information that identifies text and graphic information and natural image information, and when it is "1", it is natural image information (included in the natural image area 50). image information).

When the output signal Z5 is rOJO, it means text and figure information (image information included in the area outside the natural image area 50), and at this time, the other output signals Z4 to Zo are the color designation information of the text and figure pattern as they are. (If the color consists of two colors, black and white, it is expressed as a binary value Ml tM2, so Ml shown in 3rd FACC).

(see M2).

In the case of natural image information, the output signal Z4 read from the RAM 19 and the SP conversion circuit 25 further identifies the meaning of the information held by the other output signals Z3 to Zo.

That is, when the output signal Z4 is "1", the output signal Z3
~Zo is the high-order 4 bits as a high-efficiency code of natural image information (see Hl-H3 in Fig. 3(C), however, H1 to H3 each indicate an analog representation of the size represented by the high-order 4 bits). When it is "0", it means the lower 4 bits (3rd bit) as a high efficiency code of natural image information.
(See Figure (C) OL1 to L4, where L1 to L4 each indicate an analog representation of the brain size represented by the lower 4 bits).

In this way, the frame memory 10 of the 21st iMK stores text and graphic information and natural image information in a mixed manner, and especially in the natural image part, as mentioned earlier, there is a If the data changes rapidly after , and changes also appear in the upper 4 bits,
The upper 4 bits are stored as Hl-H3, and in cases where data changes are small and no changes are seen in the upper 4 bits, such as in flat areas of the image, only the lower 4 bits that have changed are stored. It is written as L1-L4,
They are stored together with their identification information 'r4Z4.

In the color conversion circuit 11, the CPU 1 stores color information in advance in the color conversion R and AM 31 via the multiplexer 30. For example, if the color conversion RAM 31 is a 32 x 12 bit memory, 4096 and the three primary colors red and blue are stored in the color conversion circuit 11. Each green signal is output to the switching circuit 13 as 4-bit ↑tiR.

Furthermore, in the decoding circuit 12, based on the output signal Z4 and the clock signal generated from the clock generation circuit 2, an AND circuit 37 generates a register offset signal as shown in FIG. 7 RAM memory 1 with 4 bit latch 35
The upper 4 bits of the natural image signal from 0 to 31st W(d)
The 4-bit latch 38 stores the upper 4 bits taken once.

The output signals of 4-bit latches 35 and 38 are sent to comparator 3.
8 and recognizes whether the change in the upper 4 bits is in an increasing direction or a decreasing direction.

This comparator 3 is connected to one input of the multiplexer 36.
9 is supplied with the output signal, the other input is supplied with the output signals Z3 to Zo, and the control input is supplied with the output signal Z.
4 is supplied, the output shown in the lower four bits of FIG. 3(d) is obtained as the output of the multiplexer 36.

Therefore, as natural image information, it is possible to reproduce an originally 8-bit quantized image using a 5-bit frame memory. The natural image information thus decoded into 8-bit information, which is the sum of the upper 4 bits and lower 4 bits, is output to the switching circuit 13.

The switching circuit 13 includes three multiplexers 32°33.3
4, each consisting of 4-bit color information indicating character/figure ↑ information from the color conversion circuit 11, information with the lower 4 bits set to low level L, and 8-bit natural image information from the decoding circuit 12. is the output signal Z of the frame memory 10
5 to switch and output. At this time, the multiplexers 32, 33, and 34 output red, blue, and green image information, respectively.

In the example shown in Fig. 2, the natural image is a black and white image, but if the frame memory 10 has a 16-bit configuration as in the conventional example, it has three systems of decoding circuits shown in 2-, and each By assigning red, blue, and green, alpha-coding, and supplying it to the 9J conversion circuit 13, an 8-bit digital natural color image can be reproduced.

Next, a decoding circuit for reproducing a color natural image by reducing the memory capacity ff1Th of the frame memory 10 will be described.

FIG. 4 is a proref diagram showing another specific example of the decoding circuit 12 in FIG. Further, FIG. 5 is an explanatory diagram for explaining the circuit operation of FIG. 4.

In FIG. 4, the output signals Z8 to Zo reproduced from the frame memory contain luminance information (Y) and two systems of color difference information (
The color difference information is finally converted into KGB information and supplied to the switching circuit 13.

In the same figure, 35-37 are multiplexers, 38-4
0.44 to 46 are latches, 41 to 43 are adders, 52 is an O-circuit, 47 to 48 are delay circuits that delay the signal by one clock, 49 to 50 are O-circuits, and 51 is a bistable multivibrator circuit (hereinafter referred to as (abbreviated as FF circuit), 53 is color difference RG
This is a B conversion circuit.

As is generally known, in Japan's standard television system (NTSC system), the bandwidth of the image signal is 4.
2Mtlz, color difference signal (1, Q signal or 几-
The bandwidth of Y, B-Y signal) is 1.5MHz and 0, respectively.
．． It is said to be 5MHz.

Therefore, among the natural image information, the luminance signal (Y) k8 bits and the color difference signal (B-Y, B-Y) are treated as 6-bit quantized signals, and the areas where the luminance changes are large are shown in Figure 5 (a). As shown in FIG.
In order to reproduce the luminance signal (Y) as is,
Image information is stored in the frame memory 10 so that "0" is reproduced as the output signal Z8 when the brightness change is small, that is, when it can be expressed by 4-bit brightness change information (ΔYl to ΔYa in FIG. 5(a)). Remember.

When the output signal Z8 is "0", the power signals Z3 to Zo
The K color difference signal is recorded as image information to be reproduced dot-sequentially, and at the next clock when the output signal Z8 becomes "1", the upper 4 bits of the color difference signal (CIR- in FIG. 5(a))
k""C3RY + CIB Y"C2B-y), but at the following clocks, the color difference change ↑11 report is 4 bits (ΔCIR-Y ~ ΔC2R-Y, ΔCIB in Fig. 5 (a)
-y).

Output signals Z8 to Zo as shown in Figure 5(a) above
The multiplexer 37.8-bit branch 40 and adder 43 in FIG. 4 are responsible for decoding the luminance information.

The 8-bit branch 40 receives the output signals Z7 to Z of the 7-frame memory 10 which are input via the multiplexer 37 when the output signal Z8 is 1-1.

8 bits are held as they are, and from now on, the 8 bits are set to 40.
The output signal Z7~ from the frame memory 10
Z4 is added by the adder 43, and the output signal is input again to the multiplexer 37 to reproduce the luminance information.

Further, the multiplexer 35.6 bit branch 38 and the adder 41 send the (几-Y) color difference signal, and the multiplexer 36...
The 6-bit latch 39 and adder 42 reproduce the (B-Y) color difference signals in the same manner as the luminance signals.

However, the latch clock (CK large input) supplied to the 6-bit latch 38. The clock signal supplied from the generation circuit 2 and the output signal Z8 of the frame memory 10
Q made with.

This is a signal shown as a Q output signal (however, in FIG. 5(b), only Q is shown. Q is its inverted waveform).

Furthermore, the control input of the multiplexer 35 receives the output signal Z.
8, the Z8 delay signal as shown as the output signal of the 0B circuit 49 in FIG. 5(b) generated by the delay circuit 47 and the OR circuit 49, OR circuit 5 in Figure @5 (C) created by delay circuit 48 and 0B circuit 50 based on Z8 delay signal
A signal as shown as o output signal is provided.

Furthermore, since the output signal Z8 is input to the latch inhibit input (8 manual input) of the 6-bit latch 38 and 39, when the output signal Z8 is "1", the 8-bit quantization level of the luminance signal is set to the next clock. At the timing, cB = Y) The upper 4 bits and lower 2 bits of the 6-bit m-digitization level of the color difference signal are set to 0, and at the next pk timing, (B-Y) the 6 bits of the color difference signal) fit rOJ can be recorded in the upper 4 bits and lower 2 bits of the child level.

Furthermore, at the subsequent clock table timing, the differential luminance information expressed in 4 bits and the differential color difference information expressed in 4 bits are reproduced point-sequentially, so that the 8-bit latch 40 and the 6-bit latch 38, 39 are respectively shown in FIG. C)
Information shown in can be reproduced as digital information.

As it is, there is a time lag between each piece of information, so
The 6-bit latch 44 delays the (RY) color difference information by one clock time, and the 8-bit latch 45.46 delays the luminance ts@
The time difference is corrected by delaying i by two clock times, and the result is manually input to the color difference RGB conversion circuit 53.

The color difference RGB conversion circuit 53 converts the (几-Y) color difference signal and (
Synthesize the (G-Y) color difference signals from the B-Y) color difference signals as shown in the following equation, and combine them with the luminance signals (Y signals) to create 8-bit red, green, and blue primary color signals RGB, and supply them to the switching circuit 13. do.

G-Y=-0,51(几-Y)-0,19(B-Y) Thus, by using the decoding circuit 12 as shown in FIG. While 8-bit doji natural image information is played back on a plane, 8-bit magnetized natural image information can be played back on a 9-memory plane, making it possible to reduce the memory capacity by 40 inches. .

Furthermore, the present invention is not limited to the generation level of the luminance signal being 8 bits; for example, if it is 6 bits, the memory plane required for each primary color signal in the example of FIG. is 4, resulting in 12 memory planes.On the other hand, in the example of FIG. 4, there are 7 memory planes, which can significantly reduce the memory capacity.

Furthermore, if 6-pit quantization is performed in the example shown in Figure 4, the memory capacity will be less than half that of the conventional 15-plane, 5-pit m-concentration. It is also possible to display high-quality natural images by doubling the encoding frequency.

Furthermore, in the above example, a configuration was used in which identification information between text and graphic information and natural image information was recorded in one memory brain so that the size, position, and number of natural image areas could be selected completely freely. Nature #JJ13 area is 1 in 1 screen
In the case of 4 registers, it is also possible to use 4 registers instead of the memory plane.

Each register stores horizontal start point coordinate information, end point coordinate information, vertical start point coordinate information, and end point coordinate information of the natural image area, and clock generation circuit 2 generates a clock to read out the frame memory 10. A signal indicating rectangular information can be generated on the screen by comparing the coordinates indicated by the read address information. As described above, it is obvious that the present invention is effective even in a circuit in which one memory plane is simplified.

In addition, in the example shown in Figure 1, the image information was explained as being supplied from a source other than the device, but for example, if this device is used as a display section of a device such as a small computer (personal computer) or a digital television, the image information can be supplied naturally by the device itself. The present invention can also be applied when image information is encoded and stored in a frame memory.

〔Effect of the invention〕

As described above, according to the present invention, a still image display device capable of displaying high-quality natural images with a limited memory capacity can be provided, which is effective in improving performance. In addition, when the image quality is maintained at the same level as before, it is possible to provide a still image display device that can display natural images with a smaller memory capacity, which is economical.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a still image display device as an embodiment of the present invention, Fig. 2 is a detailed circuit diagram of the main parts in Fig. 1, and Fig. 3 is a diagram for explaining the operation of Fig. 2. An explanatory diagram showing screen display examples, etc., FIG. 4 is a block diagram showing another specific column of the decoding circuit shown in FIG. 1, and FIG. 5 is a display memory output signal etc. for explaining the operation of FIG. 4. FIG. Explanation of symbols 1...CPU, 2...Clock generation circuit, 9...9J conversion M, 10...Frame memory, 11... ...Color conversion circuit, 12...
...Decoding circuit, 13...Switching circuit, 35.
...4-bit latch, 36...Multiplexer, 38...4-bit latch, 39...
...Comparator, 35-37...Multiplexer, 38-40...Latch, 41-43.
...Adder, 50...Natural painting field agent Patent attorney Akio Namiki No. 1 Totomi 3 Figure (e) Registration 0. ri-tech "L-111"
1---111 "Shi-1----Iris 4 Figure tη prayers mouth 3% Go to 13 Go to 13 Go to 13! 1
5 Figure (11) Early appearance

Claims (1)

[Scope of Claims] 1) It has a memory for storing character/graphic information and natural image information, the former as a pattern and the latter as a code, and the character/graphic information and natural image information read from the memory are sent to a display means. In the still image display device in which text and graphics and natural images are displayed on the display means in a mixed manner, the memory includes information for each piece of stored information, whether it is text or graphics information or not. First identification information for identifying whether it is image information is also stored, and for natural image information identified by the identification information, among the plurality of bits constituting one code, When compared with the previous code in chronological order, a bit at a specific position that is relatively variable (for example, the upper half or the lower half) is selected, and the second identification information indicating this is selected as a high-efficiency code. With,
In addition to storing the plurality of bits constituting the one code, when character/graphic information (pattern) is read out from the memory, color conversion means converts it into color information in units of pixels and outputs the color information. and a decoding means for converting the natural image information (high-efficiency code) back into the normal code using the second identification information and outputting the normal code when the natural image information (high-efficiency code) is read out from the memory;
The output from the color conversion means and the output from the decoding means,
A still image display device comprising: switching means for switching and outputting to the display means using first identification information given from the memory.