JPS5825769A - Picture signal processing device - Google Patents

Abstract

PURPOSE:To obtain a processing circuit where photographs and characters are synthesized very naturally, by switching a dither pattern between a photograph region and a line drawing region on an original including the photograph and the line drawing such as characters. CONSTITUTION:An input video signal 1 is quantized in an A/D converter 2 and is compared with a dither signal 6 in a comparator 4 and resulted in a video signal output. The dither signal 6 is fed from a ROM 18' where dither patterns are written, and the ROM 18' has two kinds of dither pattern in one original, and they are switched in every prescribed region by the control signal from a dither switching control line 19 and are outputted. That is, the dither pattern for the photograph region and the dither pattern for the line drawing region are switched and are applied to the comparator 4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal processing device that converts an analog input image signal into a binary signal using a dither method.

For example, in an image transmission/recording device such as a facsimile, if the output format is a binary recording format of black or white,
It is suitable for transmitting text, but not for transmitting photographs containing halftones. In order to compensate for this drawback, one set of about 4 to 32 pixels per pixel is binarized by periodically varying the threshold build level of the binarization. Conventionally, a method of expressing halftones as the area of agglomerated sunspots, that is, a systematic dither method, has been used. The gradation expression using this method is theoretically infinite, but as the gradation becomes finer, the number of pixels in a set to express that gradation increases, and the dither matrix becomes larger, resulting in pseudo-halftone dots. The disadvantage is that the grain becomes rough and difficult to see. Furthermore, when transmitting a document that contains both photos and text, if systematic dithering is used, the gradation of the photo will be transmitted correctly, but the text will be difficult to see, or conversely, if the threshold level is fixed, Binarization has contradictory drawbacks, such as characters being transmitted correctly, but photographic parts being destroyed.

FIG. 1 shows a conventional systematic dither circuit, and for the sake of simplicity, a method for obtaining four gradations will be described. 1 is a video signal input terminal into which an analog signal is input. 2 quantizes the input video signal with an A-D converter. 3 is the digital video signal line.

The number of bits for quantization is given by an integer satisfying 21≧N, assuming that the required density gradation is N gradations. For example, the number of quantization bits required to express 16 gradations of density is 4 bits. In order to make the diagram easier to read, for example, even if there are four signal lines, one signal line having the same function is indicated by a (-) symbol. (Similarly below, however, the number of signal lines is not limited to four.) 4 is a magnitude comparator, which performs a binary magnitude comparison with the signal of the comparison signal line (hereinafter referred to as dither signal line), and the result is is output to the video signal output terminal 5. Video signal output 5-0 or 1
This is a binary signal. The dither signal 6 is constituted by selecting and reading out the dither motor set by the preset switch 7°8.9 and lO. 11 is a data selector for selecting rounding, and its output signal is the dither signal 6.

Preset switch 7, 8. The order in which 9 and 10 are switched is determined by horizontal address control 11116 and vertical address control @17. 12 is a video transfer lock signal, 13 is a horizontal counter, 14 is a horizontal synchronization signal,
15 is a vertical counter. Since the dither matrix is preferably square, the number of bits y of the horizontal address control line 16 and the number of bits X of the vertical address control line 17 are made equal. In the illustrated embodiment, by setting both 11c x = y = 1, a square lattice dither matrix of 2X2 = 4 can be constructed.

FIG. 2 shows preset switches 7, 8. 9 and 1
1 instead of using 0 read-only memory (ROM)
This is a second conventional implementation method in which systematic dithering is performed by writing a dither pattern in the memory. The same functional elements as in FIG. 1 are given the same numbers. Reference numeral 18 denotes a dither matrix ROM, which has a memory capacity of, for example, Ifi 4 bytes in the illustrated embodiment. The output line of the ROM 18, that is, the number 2 of 60 bits of the dither signal line, can be set to be equal to or smaller than the number n of 30 bits output from the AD converter 2. Horizontal address control line 160
Total ij of the number of bits y and the number of bits
It can be set equal to, more than, or less than. However, the maximum gradation can be expressed at the minimum cost when n = Z = (x + y). In view of the above-mentioned drawbacks, the present invention aims to provide an image processing device that processes each area using a different dither pattern. The purpose is

Another object of the present invention is to provide an image processing device that can synthesize images and characters using a dither matrix.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 3 is a basic dither cut circuit diagram.

The same components as in FIGS. 1 and 2 are given the same numbers. For example, if two types of 2×2 dither matrices are prepared and used by switching, a ROM 18' with twice the memory capacity of the 9 dither matrix ROM 18 described in FIG. 2 is provided, and one address line is provided. and uses it as the dither switching control line 19. The dither switching control line 19 is connected to the MSB (
Programming is easy if the setting is set to MO8T 8IGNIFIOANT BIT). Therefore, by setting the dither switching control line 19 to @H'' (high level) or ``L'' (low level), it is possible to instantly switch between the two types of dither matrices. By switching the dither switching control line 19 to a predetermined value in a predetermined area, two types of dither patterns can be used in one document.

In other words, in a document containing photographs and line drawings such as characters, the dither pattern can be switched between the photograph area and the line drawing area.

Therefore, K further includes a circuit that arbitrarily sets one area,
A circuit is required to specify which dither pattern is assigned to which area.

A more detailed explanation will be given below using FIG. 4.

FIG. 4 is a block diagram of a composite dither circuit. Figure 1, tIE2 figure and! Functional elements common to those in Figure 3 are given the same numbers.

20 is a sequence controller using, for example, a micro combinator. The microcomputer used is one in which an address bus and a data bus are supplied to the outside. 21 is an address bus, and 22 is a data bus. Also, 23#i memory read/write control line, 2
4 is a direct memory access (DMA) control line via an output port with a latch function.

Each control line 21 to 24 from the sequence controller 20
are all for controlling random access memories (RAM) 28, 29 and 30.

'The RAMs 28, 29 and 30 will be referred to as a horizontal coordinate memory, 29 a vertical coordinate memory, and a dither selection memory 30 based on their respective functions.

The input data lines of each memory 28, 29 and 30 are connected to the data bus 22, and the output data lines 34.
44 and 19. The memories 28, 29 and 30 are independently selected and enabled for writing by the memory selection control +@32 from the address decoder 31, while when the DMA control line 24 is in the DMA mode, the memories 28, 29 and 30 are all selected and controlled simultaneously by a common control 41 (not shown) to be read enabled. 25, 26. and 27 are data selectors, which are connected to the address bus 21 when the DMA control @24 is not in the DMA mode. 37
,42. and 47 are data selectors 25 and 26, respectively.
．． and 27 output lines υ, and from their respective functions, 37
4 is named a dither i-trix horizontal address control line, 42 is named a dither selection memory address control line, and 47 is named a dither matrix vertical address control line. In the illustrated embodiment, the control lines 37, 42 and 47 are all 2-bit control lines, and are allocated in order from the L8B side of the address bus 21.

On the other hand, 7) "Response decoder 31q, M of address bus 21
Decode SB@. Because of this configuration, R, AM 28, 29, and 30 are allocated to a part of the memory address space of the microcomputer in the sequence controller 20, and can be accessed without distinguishing from the memory inside the sequence controller 20. can. Memo I) 2B, 29. The contents to be written in and 30 will be explained below. FIG. 5 shows the dither synthesis format. A
, -A, indicates the area, Y is the horizontal coordinate, X is the vertical coordinate,
li4, Ml, and pigeon are each region M.

In the dither matrix applied to As-A4, the outer frame E is the same as the document size in terms of address. The area is multiplied by the pigeon dither, and the 11 partial area people enclosed by the small frame are multiplied by Ml and the pigeon dither, respectively. Yfl is the horizontal coordinate of the area.

Yl and the vertical coordinate is defined as Xl)-Xi. The horizontal coordinate of area A is defined as Y, , Y, and the vertical coordinate is defined as Xs - Xs.

If the manuscript contains two photos, the coordinates ~X,,Y
, ~Y, and assign a dither suitable for the expression of Ml and Hatobusi halftones, and assign a dither suitable for the expression of letters to Hato. For example, a dither matrix as shown in FIG. 6 is written in the memory 18'. I'll leave it there. The stripes are reproduced in 166 tones,
Pigeons reproduce four tones, and pigeons reproduce binary black and white. Note that the numbers in block 60 indicate the threshold level expressed in hexadecimal.

In FIG. 4, the horizontal coordinate memory 28 stores the horizontal coordinate Y,
, Y, , right and Y, are written, and in the vertical coordinate memory 29, , X, x, and Xs are written. Also, the dither selection memo IJ3QK is the dither number area.

Write Mh and M.

In FIG. 4, the dither matrix horizontal address control line 37 is connected to the horizontal address control line 16 in the DMA mode. 33 is a horizontal position 'II core comparator which compares the horizontal coordinate memo IJlfl-7'-data@34 and the horizontal address control line 16. 35 is its horizontal coordinate con 7
(This is the output line of the horizontal coordinate comparator 33.
When there are four horizontal reference data Yn, four circuits are required, but due to the time division method, only one circuit is required. 36 is an address pull latch for this purpose, which is addressed by the dither matrix horizontal address control line 37 and latched by the video transfer lock signal 12. 38 is the output of the address pull latch 36, which is named a dither area horizontal selection line because of its function. In the illustrated embodiment, there are two dither matrix horizontal address control lines 37;
Four lines can be decoded by binary decoding in the address pull latch 36. That is, there are four dither area horizontal selection lines 38, each of which has horizontal coordinate data Y, .
Y.

Corresponding to Yt″ and Y. Dither area horizontal selection line 38
can only specify areas in the horizontal direction, such as area A1 and area A in FIG. Therefore, by taking the AND of 38 and 39, area specification in both the horizontal and vertical directions is completed. 40 is the rounding AND gate circuit, 41 is horizontal,
This is a dither area selection line that specifies areas in both vertical directions. In the DMA mode, the data selector 26 selects this dither area selection line 41, and its output line 42
is named the dither selection memory address control line because of its function.

In the illustrated embodiment, there are two dither selection memory address control lines 42, which select a pre-written dither number Ma-M* or M and output it to the dither switching control line 19. The operation of the dither matrix ROM 18 is the same as that described in FIG. Area specification in the vertical direction is in principle exactly the same as in the horizontal direction. 43 is a vertical In comparator, 44 is a vertical coordinate memory output data line, 45 is a vertical coordinate controller output line, 46 is an address supply latch, and 47 is a dither matrix vertical address control line.

Regarding the size of the dither matrix, each side is one pixel (7) 2flCn=1.2.3t 4-) (In case D, a device that can specify the area of the dither matrix is required.

An example of an XY coordinate input device for specifying an area is shown in FIGS. 7 and 8.

In FIG. 7, 145 is an XY coordinate input device manually operated by keys, 146 is its numeric keypad switch, and 147 is an X, Y coordinate input device.
, M,=, and EXCUT key +, 148 is a function key, and 149 is a light emitting indicator. With this device,
For example, if you want the coordinates of Xo to be 132 tm, use rXJr[Jr=JrlJr3Jr2JrEXOUTE
By pressing j, the light emitting display 149 displays as shown in the figure, and a numerical value corresponding to the memory 40 tc 132 m is input via the sequence controller 20. Input of other coordinates is performed in the same manner. Note that the exact key is used to officially register the value that has been temporarily registered and displayed on the display.

The XY coordinate input device shown in Fig. 8 does not input coordinates numerically;
Input is made by touching the coordinate designation area 152 on the digitizer 150 with the stylus pen 153. Therefore,
With the document placed on the coordinate designation area 152, it can be designated with the stylus pen 153. The designated area is displayed in a graph on the ORT display 154 along with characters such as Xs and Xt. The coordinates specified with the stylus pen 153 are input to the sequence controller 20 as digital values.

Note that a state in which the threshold level is constant in all cells of the dither matrix, that is, a matrix like the dove in FIG. 6 can also be considered as an example of a systematic dither matrix.

Furthermore, although an example was shown in which a dither pattern was written in the dither matrix ROM 18', it is also possible to write dither data equal to or even smaller than the minimum value of the quantized digital video signal 3, or to To,
Write dither data equal to or even greater than the maximum value of the quantized digital video signal 3, thereby making the video signal output 5 always black or always no matter how large the input video signal 1 is. Utilizing the fact that it can be made white, it is also possible to write specific characters such as internal pressure alphanumeric characters in the memory 18', like a so-called character generator, and output them as a video signal. Furthermore, in combination with the horizontal coordinate memory 28, vertical coordinate memory 29, and dither selection memory 30, it is possible to write simple sentences such as page and date on the document in real time with the reading operation. Characteristics of character output in this method are as follows. For example, an example of character output is shown in FIG.

FIG. 9 shows a special application of the dither matrix, in which the number "2" is output, for example. This rounding dither matrix is shown in FIG. As an example, the gradation is 16
The case where gradation is obtained is shown. The numbers are 4-pit binary values expressed in hex code to indicate the deterioration level. 1st
0 in Figure 8 is black regardless of the video signal level, so ``2'' in Figure 8 is black, and
Since the FJO area is white regardless of the video signal, it is possible to frame the same side of the character "2" in white.

On the other hand, in the area marked "7", the video signal is correctly binarized and displayed, so the image signal is not lost in the shaded area. In other words, it is possible to synthesize an image and a character pattern very naturally.

A concrete implementation in this case is shown in FIG. Components that are the same as those in FIG. 4 are given the same honorifics. R,0M18
In addition to the normal dither matrix, a plurality of dither matrices including character patterns as shown in FIG. 10 are stored in the memory. In addition to the normal dither matrix, the dither selection RAM 30 can select one dither matrix containing a character (rock turn) designated by the character designation device 53.

C switches the multipliers of the multipliers 50 and 51 using the character pattern control line. For example, when applying normal dither, the multiplier is set to 1. Also, when outputting a character pattern, use dither selection RA.
M30 selects a dither having a predetermined character pattern in ROM 18'.

At the same time, by controlling the control line 52, the multiplier is set to % (from K, 8 clocks of the horizontal and vertical clocks as shown in FIG. 10).
Step 61 one by one.

Therefore, one driver) 61 outputs a character pattern consisting of 8×8 pixels, and an image based on the image signal lK can be formed around the character pattern. Furthermore, by setting the control line 52 to a plurality of bits so that a plurality of multipliers can be switched, several sizes of character patterns can be selected. In other words, by setting the multiplier to 1/16, a character pattern in which one dot 61 consists of 16×16 strokes can be outputted from K.

By providing the multiplier switch in this way, the memory capacity can be reduced significantly.

The sequence controller 20 is Motorola's M6800. The data selector 25°26.27 is Texas Instruments' 8N74157. Horizontal and vertical coordinate memory 28.29. and dither selection memory 3
0.30 is Intel's I3101, horizontal and vertical coordinate comparators 33 and 43 are Texas Instruments' 8N7485, address decoder 31 is Texas Instruments' 5N7442, addressable latch 36.46 is Texas Instruments' SN74259, Texas Instruments' 8N74163 as the horizontal counter, and Texas Instruments' 5N74164 as the vertical counter. .

As described above, according to the present invention, when obtaining a reproduced image by binary recording, character recording, which places emphasis on resolution,
Rather, the conflicting problems of photographic recording, which emphasizes gradation expression ability, can be solved by using an area specifying means for specifying an area and a processing circuit for processing each area with a different dither pattern.

Furthermore, by writing character patterns into the dither matrix memory, images and characters can be synthesized very naturally.

In the illustrated embodiment, dither matrix R,
Although the method of fixing the dither pattern in 0M18' has been explained, the memories 18 and 18# may be RAMs,
In that case, other memories 28.29. and 30.30
By connecting pass lines like ', the sequential skit is a format that allows you to change the rich dither patterns available in 1220 according to the purpose of use.

Furthermore, although the address bus 21 and data bus 22 are of a type in which they are directly connected to the pass line of the microcomputer inside the sequence controller 20, they may be connected via an input/output port.

Further, in the illustrated embodiment, a case has been described in which the number of areas for specifying dither areas is two, but the number may be one or three or more.

Furthermore, although one horizontal address and one vertical address are detected in a time-division manner using one comparator 33 and 43, respectively, it is also possible to use one comparator and memory for one address data. , or a combination of both.

Further, although the vertical address counter is performed by a node square, it may also be counted by software using a microcomputer in the 7-can controller 20.

Furthermore, the functions of the horizontal coordinate memory 28, vertical ridge memory 29, dither selection memory 30, and the hardware that drives them are processed in part or in whole by software by a microcomputer in the sequence controller t20. Also good.

Further, in the illustrated embodiment, the dither matrix data is digitally compared by the magnitude comparator 4 via the dither signal line 6, but the dither signal 6 is converted from D to A without using the A to D converter 2. Alternatively, the output may be used as a reference signal of an analog comparator and converted into a binary value.

Further, although the image signal processing device according to the present invention is used at the same time as driving the reading device, it may be of a type in which the quantized video signal 3 is once stored in a storage device and then processed.

The present invention is not limited to the embodiments described above, and various modifications are possible.

[Brief explanation of drawings]

@Figure 1 is a conventional systematic dither circuit diagram, and Figure 2 is a conventional R
Fig. 3 is a dither switching circuit diagram to which the present invention can be applied; Fig. 4 is a synthetic dither circuit diagram; Fig. 5 is a diagram showing a dither synthesis format; Fig. 6 is a systematic dither circuit diagram using OM; Figure 7 shows an example of the dither matrix MotMsv.
Figure 9 shows an XY coordinate input device using a digitizer.
10 is a diagram showing the threshold value of the dither matrix for outputting the output of FIG. 8, and FIG. 11 is a diagram of a composite dither circuit for outputting the character pattern. In the figure, l is a video signal input terminal, 2 is an A/D converter, 4 is a magnitude comparator, 18' is a dither matrix ROM, 20 is a sequence controller, 2
8 is a horizontal coordinate selection memory, 29 is a vertical coordinate selection memory,
30 is a teaser selection memo IJ, and 50.51 is a multiplier. Applicant Canon Co., Ltd. L-r, 474 Figure z

Claims (1)

[Claims] Generating means for generating an image signal, character selection means for selecting a character, threshold signal generating means for generating a threshold signal, and a binarized signal by comparing the image signal and the threshold signal. and a binarization means for obtaining the minimum value of the image signal in the character portion, and the threshold signal generation means is configured to generate a minimum value of the image signal in the character portion according to the output of the character selection means.
It is characterized by outputting a small threshold signal, and outputting a threshold signal larger than the maximum value of the image signal in the vicinity of characters. Image signal processing device.