JP3234461B2 - Image data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data processing apparatus, and more particularly, to a semiconductor device in which memories for storing a plurality of types of data are integrated on the same chip and an image data processing apparatus.

[0002]

2. Description of the Related Art As shown in FIG.
A line sensor 31 is provided. Line sensor 31
Is a contact image sensor, for example, which divides a document S into a plurality of pixels P in a direction (main scanning direction) perpendicular to a paper feeding direction (sub-scanning direction) as shown in FIG. Each time, the density of each pixel P is read and output to the data converter 32 as an image signal. The facsimile is provided with a motor 33. The motor 33 is a stepping motor, and feeds the document S at predetermined intervals line by line.

[0003] A memory 34 is connected to the data converter 32. The memory 34 stores multivalued data, error data, and binary data, which will be described later. The data converter 32 converts the image signal input from the line sensor 31 into binary data based on the multi-value data and the like stored in the memory 34 and outputs the binary signal to the codec 35. The codec 35 compresses the input binary data and outputs it to the modem 36. The modem 36 inputs the compressed binary data, modulates the data, and transmits the modulated data to the destination.

[0004] Conversely, data transmitted from the other party is demodulated by the modem 36 and output to the codec 35. The codec 35 expands the input data and outputs the expanded data to the printer 37. Printer 3
Reference numeral 7 performs printing based on the input data, creates and outputs a received document.

[0005] The facsimile is provided with a CPU 38. The CPU 38 outputs a command (command) to the data converter 32, the codec 35, the modem 36, and the printer 37 based on the operation of a key (not shown) provided on the display 39 to control each of them. Also, CPU
38 controls the operation of the line sensor 31 and the motor 33 in accordance with the operation of the data converter 32.

As shown in FIG. 5, the data converter 32 is composed of components 41 to 50 and is integrated on one chip. The image signal input from the line sensor 31 is input to the analog unit 41. The image signal is an analog value, and indicates, for example, an L level when the pixel P is black, an H level when the pixel P is white, and an intermediate level when the pixel P is gray. The analog unit 41 has a predetermined number of bits (for example, 6 bits)
, And quantizes the image data to convert it into multi-value data of a plurality of gradations (64 gradations). The converted data is output to the distortion correction unit 42.

The distortion correction section 42 includes a distortion correction memory section 43
The distortion correction data stored in advance is read out, the gradation correction is performed on the input multi-value data for one line based on the distortion correction data, and the multi-value data of the correction result is output to the gamma correction unit 44. I do. The distortion correction data (shading data) is data for numerically correcting distortion generated in the optical system. The distortion correction data is created such that, for example, a white reference plate is captured by the line sensor 31 and all the multi-valued data for one line quantized by the analog unit 41 at that time have the same value.

The gamma correction section 44 reads out gamma correction data stored in advance in the gamma correction memory section 45 and performs gamma correction on the multi-valued data input from the distortion correction section 42 based on the gamma correction data. The multi-value data of the correction result is output to the filter unit 46. The gamma correction data is for correcting a deviation between a photoelectric conversion characteristic of the line sensor 31 and a change in the intensity of light that a person actually visually recognizes.

A filter unit 46 is a spatial filter composed of a 3 × 3 matrix based on the multi-valued data for two lines stored in the memory 34 and the multi-valued data for one line input from the gamma correction unit 44. And converts the filtered multi-valued data into a binarizing unit 47 or a halftone unit 48.
Output to This spatial filter performs filter processing such as edge enhancement and smoothing on multi-valued data. Further, the filter unit 46 sequentially rewrites the previous one-line multi-value data among the two-line multi-value data stored in the memory 34 into newly input one-line multi-value data. As a result, the multi-valued data for two lines, that is, the newly input multi-valued data for one line and the multi-valued data for the previous one line, is stored in the memory 34.

[0010] binarization unit 47 converts the binary data based on a preset threshold multivalued data input,
Output to the resolution converter 49. On the other hand, the halftone section 48
Error diffusion processing is performed on the input multi-value data, and 2
Generate value data. The error diffusion process is for expressing the halftone of the input multi-valued data in a pseudo manner, and adds an error generated when the multi-valued data is binarized to the multi-valued data of peripheral pixels. ing. At this time, the error data is temporarily stored in the memory 34.

The resolution conversion unit 49 reads the binary data corresponding to pixels P of one line stored in the memory 34, input from the binarization unit 47 or the halftone area 48 on the basis of the binary data Reduction processing is performed on the binary data according to the size of the document S, and the processing result is output to the output control unit 50. The reduction process is performed to reduce the amount of data to be transmitted to the destination by thinning out the binary data at a predetermined line interval. At this time, in order to prevent a graphic (for example, a thin line in the main scanning direction or the double scanning direction) from being completely erased by thinning data,
The resolution conversion unit 49 is configured to correlate a plurality of multi-value data.

The output control section 50 controls and outputs the format of the binary data in accordance with the codec 35 and the modem 36. As shown in FIG. 7, the memory 34 stores, for example, S
It is composed of a RAM, and is divided into areas of a line memory 34a, 34b, an error memory 34c, and a reduced memory 34d. In each of the line memories 34a and 34b, multi-value data for one line used in the processing of the filter unit 46 is stored. The error memory 34c stores a necessary amount of error data used in the processing of the halftone section 48. The reduction memory 34d stores binary data corresponding to one line of pixels P used in the processing of the resolution converter 49.

Since the data amount of each data differs depending on the size of the original S to be taken, each of the memories 34a to 34d
Is set to a capacity capable of storing the data amount of each data corresponding to the maximum size of the document S that can be handled by facsimile. If the maximum original S that can be handled by the facsimile is, for example, B4 size, the number of pixels for one line is about 200
This is set to 0, and an SRAM having a word configuration of 8K words × 8 bits (1K words = 1024 words) is adopted as the memory 38 in response to this. Each of the memories 34a to 34d is assigned a word number corresponding to the maximum size of the document S, for example, 2K words.

The data converter 32 sequentially performs processing from the left side pixel P to the right side pixel P of the document S along the main scanning direction due to the nature of image processing. Multi-value data, error data, and binary data for the pixel P are sequentially stored from the start address.

[0015]

By the way, in order to form a 3 × 3 matrix in the filter section 46, multi-line data of two lines of the document S is required. In order for the halftone section 48 to perform the error diffusion process in the sub-scanning direction, error data corresponding to at least one line of pixels P is required. Then, in order to perform the reduction processing in the resolution conversion unit 49, two pixels corresponding to the pixels P for one line are used.
Value data is required. Therefore, the data converter 32
Is used when processing image data for one line.
It is necessary to read multi-value data, error data and binary data from 4 respectively. However, the data converter 32
It is difficult to perform high-speed operations because data stored at different addresses must be read out by sequentially specifying the address corresponding to each data in a time-division manner.
Processing of an address generation circuit (not shown) is complicated. As a result, there is a problem that the circuit scale of the data converter 32 increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device and an image data processing device capable of reducing costs.

According to a first aspect of the present invention, there is provided an analog section (41) for fetching image data composed of a plurality of lines on a line-by-line basis, quantizing the image data of each line for each pixel, and converting the image data into multi-valued data. Quantized multi-valued data for one line and multi-valued data for a plurality of lines stored in advance
A spatial filter based on the multi-valued one line
A filter unit (46) for performing a filtering process on the data based on the spatial filter;
Input multi-value data for the line, and
Error data calculated in the error diffusion process
Halftone section (48) for generating binary data corresponding to a key
And a resolution conversion unit that performs a reduction process on the binary data input from the halftone unit (48) to reduce the data amount of the binary data with reference to the binary data of another line stored in advance. (49) and the total number of bits of the multi-value data, error data, and binary data required for the processing of the filter unit (46), the halftone unit (48), and the resolution conversion unit (49) Formed into a word structure consisting of
The deviated data is temporarily stored, and each part (46, 48, 4
The point is that the data memory section (2) from which the data is read and written simultaneously from 9) is formed on the same semiconductor substrate.

According to a second aspect of the present invention, in the image data processing apparatus according to the first aspect, the data memory section comprises a DRAM, and the filter section, the halftone section, and the resolution conversion section include the DRAM. The gist is that the data memory unit is accessed at intervals shorter than the refresh interval.

Therefore, according to the first aspect of the present invention,
On the same semiconductor chip, analog part, filter part,
A halftone section, a resolution conversion section, and a data memory section are formed. The analog section captures image data composed of a plurality of lines in units of one line, and the image data of each line is quantized for each pixel and converted into multi-valued data. The quantized multi-valued data for one line is input to the filter unit, and based on the multi-valued data for a plurality of lines stored in advance, filtering is performed on the input multi-valued data for one line. Done. One line of multi-valued data after filtering is input to the halftone portion, and the input filtered multi-valued data is converted into binary data based on error data stored in advance. The binary data converted by the halftone unit is input to the resolution conversion unit,
Reduction processing is performed on the input binary data based on the binary data stored in advance to reduce the data amount of the binary data. The data memory unit is formed in a word configuration composed of the total number of bits of each of multi-value data, error data, and binary data necessary for processing of the filter unit, the halftone unit, and the resolution conversion unit. Is temporarily stored, and the data is read and written from each unit at the same time.

According to the second aspect of the present invention, the data memory section is composed of a DRAM, and the filter section, the halftone section, and the resolution conversion section are connected to the data memory section at intervals shorter than the refresh interval of the DRAM. Access is made to it.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. In the present embodiment, the same components as those of the conventional example shown in FIGS. 4 to 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

FIG. 2 is a schematic configuration diagram of the facsimile of the present embodiment, and FIG. 1 is a block circuit diagram of the data converter 1 of the present embodiment. This embodiment differs from the conventional example in the following points.

[1] The data converter 32 of the conventional example is replaced by the data converter 1 in the present embodiment. [2] The memory 34 of the conventional example is built in the data converter 1 as the data memory unit 2 in this embodiment.

The data memory unit 2 is composed of a DRAM. The line memories 3 and 4 storing multi-value data for one line used in the processing of the filter unit 46 and the error data used in the processing of the halftone unit 48 are stored in the data memory unit 2. The error memory 5 to be stored and 1 used in the processing of the resolution conversion unit 49
It is divided into areas of the reduced memory 6 in which binary data corresponding to the pixels P for the line are stored.

As shown in FIG. 3, the data memory unit 2
For example, it is formed in a word configuration of 2K words × 21 bits. The data memory unit 2 reads and writes 21-bit data by designating one address in one access. Here, of the 21 bits of the data memory unit 2, the first 6 bits are allocated to the line memory 3, the next 6 bits are allocated to the line memory 4, and the next 8 bits are allocated to the error memory 5, The last one bit is allocated to the reduction memory 6. That is, the data memory unit 2 has a word configuration composed of the total number of bits constituting each data based on the configuration of the multi-value data, error data, and binary data stored in the data memory unit 2. Is formed.

In the data memory unit 2, one data stored in each of the memories 3 to 6 is simultaneously specified for one address, so that the error is different from the line memories 3 and 4 for one access. From the memory 5 and the reduced memory 6, two multi-valued data, one error data, and one binary data can be read / written in total of four data. In other words, only one access to the data memory unit 2 allows reading and writing of each data necessary for the processing of the units 46, 48, and 49. Therefore, since the number of accesses to the data memory unit 2 is reduced, writing and reading of each data to and from the data memory unit 2 can be performed at high speed. Further, since the processing of the address generation circuit (not shown) is simplified, it is possible to prevent the circuit scale of the data converter 1 from increasing.

Filter section 46 constituting a spatial filter
Is such that multi-value data for one line input from the gamma correction unit 44 is alternately written to the line memories 3 and 4. For example, when the filter unit 46 performs the filtering process on the multi-value data of the n-th line, the multi-value data of the (n−1) -th line is stored in the line memory 3, and the n-th line of the n-th line is stored in the line memory 4. Multi-value data is stored. The filter unit 46 performs a filter operation based on the multivalued data of the (n + 1) th line sequentially input and the multivalued data of the (n−1) th and nth lines read from the line memories 3 and 4. At this time, the filter unit 46
Rewrites the multivalued data of the (n-1) th line stored in the line memory 3 sequentially into the multivalued data of the (n + 1) th line. Then, the multi-valued data of the n-th and (n + 1) -th lines respectively stored in the line memories 3 and 4 are as follows:
It is read out when the multi-value data of the next (n + 1) th line is processed by the filter unit 46.

First, the halftone section 48 for performing the error diffusion process reads out the error data from the error memory 5 and adds it to the multi-valued data to be binarized. Then, the multivalued data to which the error data has been added is binarized, and the error generated at that time is written to the error memory 5. When the error diffusion processing is performed in the horizontal direction (main scanning direction), error data corresponding to an appropriate number of pixels is stored in the error memory 5. Error data corresponding to the pixel is stored in the error memory 5. In other words, in order to add an error generated by binarizing the multi-value data of a certain pixel to the multi-value data of the surrounding pixels (error diffusion), it is necessary to wait until the multi-value data of the pixel to be added is input. Interval, error memory 5
Is stored with error data. For example, when error diffusion processing is performed on the multi-value data of the n-th line by one pixel in the vertical direction, the error data of one line generated from the multi-value data of the (n-1) -th line is stored in the error memory 5. , And are sequentially read in accordance with the multi-value data of the n-th line. Then, the error data generated from the multi-level data of the n-th line is newly written in the error memory 5.

Each time the resolution conversion unit 49 performs the reduction process on the binary data for one line, the resolution conversion unit 49 reads the binary data for one line from the reduction memory 6 and reads the binary data for a new line. And writing of binary data. For example, to reduce the binary data of the n-th line, n-
The binary data of the first line is stored in the reduction memory 6, the binary data of the (n-1) th line is read out, and the binary data of the nth line is reduced. The (n-1) th binary data is sequentially rewritten to the nth binary data.

The filter section 46, the halftone section 48, and the resolution conversion section 49 read and write the data required for processing in the memories 3 to 6 line by line. The number of data for one line from which reading / writing is performed from each of the units 46, 48, and 49 is represented by CP
It is determined according to the width of the document S according to an instruction from U38.

For example, if the number of multi-value data for one line is one,
When 000 is specified, addresses from 0 to 1K words are accessed for the data memory unit 2 in which a capacity of 2K words is set. Here, the data memory unit 2 has a DRA that requires a data refresh operation.
Because of the configuration of M, the refresh operation is performed on the address where the data is stored. Generally, the refresh operation of the DRAM is performed for all addresses. However, in the data memory unit 2, since the address for storing data is biased to a predetermined range, if the refresh operation is performed only within that range. It will be good. For example, when data is stored in addresses from 0 to 1K words as described above, 0 to 1K words are stored.
The refresh operation is performed only for addresses up to K words, and the refresh operation is not necessary for addresses after 1K words. In the DRAM, since writing and reading of data is a refresh operation, the interval at which the units 46, 48, and 49 write and read data to and from the memories 2 to 6 is equal to DRA.
If M is shorter than the required refresh interval, the refresh operation itself is not required.

As described above, according to the facsimile of the present embodiment, the following operations and effects can be obtained. Bits obtained by summing the data memory unit 2 to the bit numbers of the multi-value data for one line, the error data, and the binary data for one line stored in the line memories 3 and 4, the error memory 5, and the reduction memory 7 Word structure consisting of numbers. As a result, two multi-value data, 1
Error data and one binary data at the same time
Writing can be performed, and the number of accesses to the data memory unit 2 can be reduced. Therefore,
Writing and reading of a plurality of data to and from the data memory unit 2 can be performed at high speed. In other words, a memory with a low operation speed can be used. In addition, since the processing of an address generation circuit (not shown) is simplified, the data converter 1
Can be prevented from increasing in circuit scale.

The line memories 3 and 3 of the data memory unit 2
In the error memory 5, the error memory 5, and the reduction memory 6, the multi-value data or the binary data stored therein are rewritten each time the data of the pixels P for one line is processed. That is, multi-valued data or binary data required for the processing of the filter unit 46, the halftone unit 48, and the resolution conversion unit 49 is used for the distortion correction data or the gamma correction data used by the distortion correction unit 42 and the gamma correction unit 44. There is no need to hold for a long time. For this reason, it is not necessary to use an SRAM for the data memory unit 2, and the data is automatically lost with time.
A RAM can be used, and the chip area of the data memory unit 2 can be reduced.

If the data memory unit 2 and the data converter 1 are integrated on the same chip, it is not necessary to provide an input / output terminal for connecting the data memory unit 2 and the data converter 1. Therefore, unlike the conventional data converter 32, an input / output terminal is not required to connect to the memory 34, and the peripheral circuits of the data converter 1 can be simplified accordingly.

The present invention may be carried out as follows in addition to the above embodiment. 1) In the above embodiment, the number of pixels for one line is approximately 2000
(2K), but may be implemented with any number of pixels such as 4K, 8K, and the like.

2) In the above embodiment, the multi-valued data required for the processing of the filter unit 46 is 6 bits, and the error data required for the processing of the halftone unit 48 is 8 bits. May be changed to practice. At this time, it goes without saying that the word configuration of the data memory unit 2 is changed in accordance with the changed number of bits of the multi-value data.

3) In the above embodiment, the halftone section 48 uses the error diffusion process as the halftone process to convert the halftone into two.
Although the data is converted into the value data, the data may be converted into the binary data using a dither method or the like.

4) In the above embodiment, the filter unit 46 creates a spatial filter composed of a 3 × 3 matrix and performs the filtering process. However, a spatial filter of a matrix other than the 3 × 3 matrix is created and the filtering process is performed. May be performed. In that case, the line memories 3 and 4
Further, one or more line memories are added to store multi-value data of a plurality of lines.

5) In the above embodiment, the error memory 5 for storing the error data corresponding to the pixels P for one line is provided, and the error diffusion processing is performed based on the error data. An error memory for storing error data corresponding to the pixel P may be provided, and error diffusion processing may be performed based on the error data.

6) In the above embodiment, the reduction memory 6 for storing the binary data corresponding to the pixels P for one line is provided, and the reduction processing is performed based on the binary data.
A reduction memory for storing binary data corresponding to the pixels P for a plurality of lines may be provided, and the reduction processing may be performed based on the binary data.

7) In the above embodiment, the distortion correction memory unit 43 and the gamma correction memory unit 45 may be configured to be able to read and write correction data from outside the data converter 1, respectively. For example, the memory unit 4
The correction data stored in 3, 45 is read, and arbitrary correction data is created based on the correction data. The created correction data is stored in the memory units 43 and 45, and the distortion correction unit 42 and the gamma correction unit 44 perform correction processing based on the stored correction data.

8) In the above embodiment, each of the distortion correction memory unit 43 and the gamma correction memory unit 45 is a well-known ROM.
(PROM, EEPROM, etc.) may be used to store distortion correction data or gamma correction data.

9) In the above embodiment, the image data processing apparatus is embodied as a facsimile.
It may be embodied in R or the like. While the embodiments of the present invention have been described above, technical ideas other than the claims that can be grasped from the embodiments will be described below together with their effects.

(B) In the image data processing device according to the first or second aspect, the halftone section performs an error diffusion process on the input multi-value data, and stores the error data in the data memory section. Data processing device. According to this configuration, it is possible to easily convert the multi-value data of the halftone pixel P into binary data.

(B) In the image data processing apparatus of (1) or (2), the output control section (50) for controlling the format of binary data for the codec (35) and the modem (36) connected to the outside is the same. An image data processing device formed on a semiconductor chip. According to this configuration, it is possible to easily control and output the format of the binary data.

[0046]

As described in detail above, according to the present invention, it is possible to provide a semiconductor device and an image data processing device capable of reducing costs.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a data converter according to an embodiment.

FIG. 2 is a schematic configuration diagram of a facsimile according to the embodiment.

FIG. 3 is an explanatory diagram showing an area of a data memory according to the embodiment;

FIG. 4 is a schematic configuration diagram of a conventional facsimile.

FIG. 5 is a block circuit diagram of a conventional data converter.

FIG. 6 is an explanatory diagram showing pixels of a facsimile document.

FIG. 7 is an explanatory diagram showing an area of each data stored in a conventional memory.

[Explanation of symbols]

 2 Data memory unit 41 Analog unit 46 Filter unit 48 Halftone unit 49 Resolution conversion unit

Claims (2)

(57) [Claims] An analog section for fetching image data composed of a plurality of lines on a line-by-line basis, quantizing the image data of each line for each pixel, and converting the image data into multi-valued data;
And one-line quantized multi-valued data and stored in advance
Spatial filter based on multi-valued data for multiple lines
The space for the multi-valued data for one line.
Filter unit (4) that performs filter processing based on a filter
6), multi-valued data for one line after the filtering process is input, and the multi-valued data is calculated by an error diffusion process.
Error data is added to generate binary data corresponding to halftone.
With reference to the halftone part (48) to be formed and the binary data of another line stored in advance, the binary data input from the halftone part (48) is subjected to a reducing process to reduce the binary data. A resolution conversion unit (49) for reducing the data amount; multi-valued data, error data, and binary data required for processing by the filter unit (46), the halftone unit (48), and the resolution conversion unit (49), respectively A data memory unit (2) which is formed in a word configuration consisting of the total number of bits, temporarily stores the changed data, and reads and writes these data simultaneously from each unit (46, 48, 49). Are formed on the same semiconductor substrate. 2. The image data processing device according to claim 1, wherein said data memory unit (2) comprises a DRAM, said filter unit (46), a halftone unit (48), and a resolution conversion unit (49). Is an image data processing device which accesses the data memory section (2) at intervals shorter than the refresh interval of the DRAM.